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Issue 2252863003: [turbofan] Add Float32(Max|Min) machine operators. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Type is number now. Created 4 years, 4 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #if V8_TARGET_ARCH_X64 5 #if V8_TARGET_ARCH_X64
6 6
7 #include "src/base/bits.h" 7 #include "src/base/bits.h"
8 #include "src/base/division-by-constant.h" 8 #include "src/base/division-by-constant.h"
9 #include "src/bootstrapper.h" 9 #include "src/bootstrapper.h"
10 #include "src/codegen.h" 10 #include "src/codegen.h"
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2875 2875
2876 void MacroAssembler::Movq(Register dst, XMMRegister src) { 2876 void MacroAssembler::Movq(Register dst, XMMRegister src) {
2877 if (CpuFeatures::IsSupported(AVX)) { 2877 if (CpuFeatures::IsSupported(AVX)) {
2878 CpuFeatureScope scope(this, AVX); 2878 CpuFeatureScope scope(this, AVX);
2879 vmovq(dst, src); 2879 vmovq(dst, src);
2880 } else { 2880 } else {
2881 movq(dst, src); 2881 movq(dst, src);
2882 } 2882 }
2883 } 2883 }
2884 2884
2885 void MacroAssembler::Movmskps(Register dst, XMMRegister src) {
2886 if (CpuFeatures::IsSupported(AVX)) {
2887 CpuFeatureScope scope(this, AVX);
2888 vmovmskps(dst, src);
2889 } else {
2890 movmskps(dst, src);
2891 }
2892 }
2885 2893
2886 void MacroAssembler::Movmskpd(Register dst, XMMRegister src) { 2894 void MacroAssembler::Movmskpd(Register dst, XMMRegister src) {
2887 if (CpuFeatures::IsSupported(AVX)) { 2895 if (CpuFeatures::IsSupported(AVX)) {
2888 CpuFeatureScope scope(this, AVX); 2896 CpuFeatureScope scope(this, AVX);
2889 vmovmskpd(dst, src); 2897 vmovmskpd(dst, src);
2890 } else { 2898 } else {
2891 movmskpd(dst, src); 2899 movmskpd(dst, src);
2892 } 2900 }
2893 } 2901 }
2894 2902
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5815 movl(rax, dividend); 5823 movl(rax, dividend);
5816 shrl(rax, Immediate(31)); 5824 shrl(rax, Immediate(31));
5817 addl(rdx, rax); 5825 addl(rdx, rax);
5818 } 5826 }
5819 5827
5820 5828
5821 } // namespace internal 5829 } // namespace internal
5822 } // namespace v8 5830 } // namespace v8
5823 5831
5824 #endif // V8_TARGET_ARCH_X64 5832 #endif // V8_TARGET_ARCH_X64
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