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Side by Side Diff: src/compiler/arm64/code-generator-arm64.cc

Issue 2252863003: [turbofan] Add Float32(Max|Min) machine operators. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Type is number now. Created 4 years, 4 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/compiler/code-generator.h" 5 #include "src/compiler/code-generator.h"
6 6
7 #include "src/arm64/frames-arm64.h" 7 #include "src/arm64/frames-arm64.h"
8 #include "src/arm64/macro-assembler-arm64.h" 8 #include "src/arm64/macro-assembler-arm64.h"
9 #include "src/ast/scopes.h" 9 #include "src/ast/scopes.h"
10 #include "src/compiler/code-generator-impl.h" 10 #include "src/compiler/code-generator-impl.h"
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1356 // TODO(dcarney): implement directly. See note in lithium-codegen-arm64.cc 1356 // TODO(dcarney): implement directly. See note in lithium-codegen-arm64.cc
1357 FrameScope scope(masm(), StackFrame::MANUAL); 1357 FrameScope scope(masm(), StackFrame::MANUAL);
1358 DCHECK(d0.is(i.InputDoubleRegister(0))); 1358 DCHECK(d0.is(i.InputDoubleRegister(0)));
1359 DCHECK(d1.is(i.InputDoubleRegister(1))); 1359 DCHECK(d1.is(i.InputDoubleRegister(1)));
1360 DCHECK(d0.is(i.OutputDoubleRegister())); 1360 DCHECK(d0.is(i.OutputDoubleRegister()));
1361 // TODO(dcarney): make sure this saves all relevant registers. 1361 // TODO(dcarney): make sure this saves all relevant registers.
1362 __ CallCFunction(ExternalReference::mod_two_doubles_operation(isolate()), 1362 __ CallCFunction(ExternalReference::mod_two_doubles_operation(isolate()),
1363 0, 2); 1363 0, 2);
1364 break; 1364 break;
1365 } 1365 }
1366 case kArm64Float32Max: {
1367 __ Fmax(i.OutputFloat32Register(), i.InputFloat32Register(0),
1368 i.InputFloat32Register(1));
1369 break;
1370 }
1366 case kArm64Float64Max: { 1371 case kArm64Float64Max: {
1367 __ Fmax(i.OutputDoubleRegister(), i.InputDoubleRegister(0), 1372 __ Fmax(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
1368 i.InputDoubleRegister(1)); 1373 i.InputDoubleRegister(1));
1369 break; 1374 break;
1370 } 1375 }
1376 case kArm64Float32Min: {
1377 __ Fmin(i.OutputFloat32Register(), i.InputFloat32Register(0),
1378 i.InputFloat32Register(1));
1379 break;
1380 }
1371 case kArm64Float64Min: { 1381 case kArm64Float64Min: {
1372 __ Fmin(i.OutputDoubleRegister(), i.InputDoubleRegister(0), 1382 __ Fmin(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
1373 i.InputDoubleRegister(1)); 1383 i.InputDoubleRegister(1));
1374 break; 1384 break;
1375 } 1385 }
1376 case kArm64Float64Abs: 1386 case kArm64Float64Abs:
1377 __ Fabs(i.OutputDoubleRegister(), i.InputDoubleRegister(0)); 1387 __ Fabs(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
1378 break; 1388 break;
1379 case kArm64Float64Neg: 1389 case kArm64Float64Neg:
1380 __ Fneg(i.OutputDoubleRegister(), i.InputDoubleRegister(0)); 1390 __ Fneg(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
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2075 padding_size -= kInstructionSize; 2085 padding_size -= kInstructionSize;
2076 } 2086 }
2077 } 2087 }
2078 } 2088 }
2079 2089
2080 #undef __ 2090 #undef __
2081 2091
2082 } // namespace compiler 2092 } // namespace compiler
2083 } // namespace internal 2093 } // namespace internal
2084 } // namespace v8 2094 } // namespace v8
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