Add the new @llvm.nacl.atomic.fence.all intrinsic

test/Transforms/NaCl/atomics.ll

-; RUN: opt -nacl-rewrite-atomics -S < %s | FileCheck %s
+; RUN: opt -nacl-rewrite-atomics -remove-asm-memory -S < %s | FileCheck %s
 
 ; Each of these tests validates that the corresponding legacy GCC-style
 ; builtins are properly rewritten to NaCl atomic builtins. Only the
 ; GCC-style builtins that have corresponding primitives in C11/C++11 and
 ; which emit different code are tested. These legacy GCC-builtins only
 ; support sequential-consistency.
 ;
 ; test_* tests the corresponding __sync_* builtin. See:
 ; http://gcc.gnu.org/onlinedocs/gcc-4.8.1/gcc/_005f_005fsync-Builtins.html
 ;
@@ skipping 191 matching lines @@
 }
 
 ; CHECK: @test_val_compare_and_swap_i64
 define i64 @test_val_compare_and_swap_i64(i64* %ptr, i64 %oldval, i64 %newval) {
   ; CHECK-NEXT: %res = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %oldval, i64 %newval, i32 6, i32 6)
   ; CHECK-NEXT: ret i64 %res
   %res = cmpxchg i64* %ptr, i64 %oldval, i64 %newval seq_cst
   ret i64 %res
 }
 
-; CHECK: @test_synchronize
-define void @test_synchronize() {
+; This patterns gets emitted by C11/C++11 atomic thread fences.
+;
+; CHECK: @test_c11_fence
+define void @test_c11_fence() {
   ; CHECK-NEXT: call void @llvm.nacl.atomic.fence(i32 6)
   ; CHECK-NEXT: ret void
   fence seq_cst
   ret void
 }
 
+; This pattern gets emitted for ``__sync_synchronize`` and
+; ``asm("":::"memory")`` when Clang is configured for NaCl.
+;
+; CHECK: @test_synchronize
+define void @test_synchronize() {
+  ; CHECK-NEXT: call void @llvm.nacl.atomic.fence.all()
+  ; CHECK-NEXT: ret void
+  call void asm sideeffect "", "~{memory}"()
+  fence seq_cst
+  call void asm sideeffect "", "~{memory}"()
+  ret void
+}
+
+; Make sure the above pattern is respected and not partially-matched.
+;
+; CHECK: @test_synchronize_bad1
+define void @test_synchronize_bad1() {
+  ; CHECK-NOT: call void @llvm.nacl.atomic.fence.all()
+  call void asm sideeffect "", "~{memory}"()
+  fence seq_cst
+  ret void
+}
+
+; CHECK: @test_synchronize_bad2
+define void @test_synchronize_bad2() {
+  ; CHECK-NOT: call void @llvm.nacl.atomic.fence.all()
+  fence seq_cst
+  call void asm sideeffect "", "~{memory}"()
+  ret void
+}
+
 ; CHECK: @test_lock_test_and_set_i8
 define zeroext i8 @test_lock_test_and_set_i8(i8* %ptr, i8 zeroext %value) {
   ; CHECK-NEXT: %res = call i8 @llvm.nacl.atomic.rmw.i8(i32 6, i8* %ptr, i8 %value, i32 6)
   ; CHECK-NEXT: ret i8 %res
   %res = atomicrmw xchg i8* %ptr, i8 %value seq_cst
   ret i8 %res
 }
 
 ; CHECK: @test_lock_release_i8
 define void @test_lock_release_i8(i8* %ptr) {
@@ skipping 231 matching lines @@
 
 ; CHECK: @test_volatile_store_v4i16
 define void @test_volatile_store_v4i16(<4 x i16>* %ptr, <4 x i16> %value) {
   ; CHECK-NEXT: %ptr.cast = bitcast <4 x i16>* %ptr to i64*
   ; CHECK-NEXT: %value.cast = bitcast <4 x i16> %value to i64
   ; CHECK-NEXT: call void @llvm.nacl.atomic.store.i64(i64 %value.cast, i64* %ptr.cast, i32 6)
   ; CHECK-NEXT: ret void
   store volatile <4 x i16> %value, <4 x i16>* %ptr, align 8
   ret void
 }