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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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1913 rxy_form(AG, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1913 rxy_form(AG, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1914 } | 1914 } |
1915 | 1915 |
1916 // Add Register-Storage (64<-32) | 1916 // Add Register-Storage (64<-32) |
1917 void Assembler::agf(Register r1, const MemOperand& opnd) { | 1917 void Assembler::agf(Register r1, const MemOperand& opnd) { |
1918 rxy_form(AGF, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 1918 rxy_form(AGF, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
1919 } | 1919 } |
1920 | 1920 |
1921 // Add Immediate (64) | 1921 // Add Immediate (64) |
1922 void Assembler::agfi(Register r1, const Operand& opnd) { | 1922 void Assembler::agfi(Register r1, const Operand& opnd) { |
1923 ril_form(ALFI, r1, opnd); | 1923 ril_form(AGFI, r1, opnd); |
1924 } | 1924 } |
1925 | 1925 |
1926 // Add Register-Register (64<-32) | 1926 // Add Register-Register (64<-32) |
1927 void Assembler::agfr(Register r1, Register r2) { rre_form(AGFR, r1, r2); } | 1927 void Assembler::agfr(Register r1, Register r2) { rre_form(AGFR, r1, r2); } |
1928 | 1928 |
1929 // Add Halfword Immediate (64) | 1929 // Add Halfword Immediate (64) |
1930 void Assembler::aghi(Register r1, const Operand& i2) { ri_form(AGHI, r1, i2); } | 1930 void Assembler::aghi(Register r1, const Operand& i2) { ri_form(AGHI, r1, i2); } |
1931 | 1931 |
1932 // Add Halfword Immediate (64) | 1932 // Add Halfword Immediate (64) |
1933 void Assembler::aghik(Register r1, Register r3, const Operand& i2) { | 1933 void Assembler::aghik(Register r1, Register r3, const Operand& i2) { |
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2639 // Insert Immediate (low high) | 2639 // Insert Immediate (low high) |
2640 void Assembler::iilh(Register r1, const Operand& opnd) { | 2640 void Assembler::iilh(Register r1, const Operand& opnd) { |
2641 ri_form(IILH, r1, opnd); | 2641 ri_form(IILH, r1, opnd); |
2642 } | 2642 } |
2643 | 2643 |
2644 // Insert Immediate (low low) | 2644 // Insert Immediate (low low) |
2645 void Assembler::iill(Register r1, const Operand& opnd) { | 2645 void Assembler::iill(Register r1, const Operand& opnd) { |
2646 ri_form(IILL, r1, opnd); | 2646 ri_form(IILL, r1, opnd); |
2647 } | 2647 } |
2648 | 2648 |
| 2649 // Load Immediate 32->64 |
| 2650 void Assembler::lgfi(Register r1, const Operand& opnd) { |
| 2651 ril_form(LGFI, r1, opnd); |
| 2652 } |
| 2653 |
2649 // GPR <-> FPR Instructions | 2654 // GPR <-> FPR Instructions |
2650 | 2655 |
2651 // Floating point instructions | 2656 // Floating point instructions |
2652 // | 2657 // |
2653 // Load zero Register (64) | 2658 // Load zero Register (64) |
2654 void Assembler::lzdr(DoubleRegister r1) { | 2659 void Assembler::lzdr(DoubleRegister r1) { |
2655 rre_form(LZDR, Register::from_code(r1.code()), Register::from_code(0)); | 2660 rre_form(LZDR, Register::from_code(r1.code()), Register::from_code(0)); |
2656 } | 2661 } |
2657 | 2662 |
2658 // Add Register-Register (LB) | 2663 // Add Register-Register (LB) |
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3118 SKIP_ICACHE_FLUSH); | 3123 SKIP_ICACHE_FLUSH); |
3119 } | 3124 } |
3120 | 3125 |
3121 reloc_info_writer.Write(&rinfo); | 3126 reloc_info_writer.Write(&rinfo); |
3122 } | 3127 } |
3123 } | 3128 } |
3124 | 3129 |
3125 } // namespace internal | 3130 } // namespace internal |
3126 } // namespace v8 | 3131 } // namespace v8 |
3127 #endif // V8_TARGET_ARCH_S390 | 3132 #endif // V8_TARGET_ARCH_S390 |
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