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Unified Diff: src/arm/disasm-arm.cc

Issue 223623003: Fix fixed-point vcvt_f64_s32 immediate value encoding (Closed) Base URL: git://github.com/v8/v8.git@master
Patch Set: Reorder bits for clarity Created 6 years, 9 months ago
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Index: src/arm/disasm-arm.cc
diff --git a/src/arm/disasm-arm.cc b/src/arm/disasm-arm.cc
index aa8ee22b73a3c4e7b92ea3312e7bd5b3da8bf96a..c918f90e9142d2f2c64b1e597e0c4f5fae4fc696 100644
--- a/src/arm/disasm-arm.cc
+++ b/src/arm/disasm-arm.cc
@@ -1272,7 +1272,7 @@ void Decoder::DecodeTypeVFP(Instruction* instr) {
} else if ((instr->Opc2Value() == 0xA) && (instr->Opc3Value() == 0x3) &&
(instr->Bit(8) == 1)) {
// vcvt.f64.s32 Dd, Dd, #<fbits>
- int fraction_bits = 32 - ((instr->Bit(5) << 4) | instr->Bits(3, 0));
+ int fraction_bits = 32 - ((instr->Bits(3, 0) << 1) | instr->Bit(5));
Format(instr, "vcvt'cond.f64.s32 'Dd, 'Dd");
out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
", #%d", fraction_bits);
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