Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(650)

Side by Side Diff: src/arm/disasm-arm.cc

Issue 223623003: Fix fixed-point vcvt_f64_s32 immediate value encoding (Closed) Base URL: git://github.com/v8/v8.git@master
Patch Set: Reorder bits for clarity Created 6 years, 8 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « src/arm/assembler-arm.cc ('k') | src/arm/simulator-arm.cc » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
(...skipping 1254 matching lines...) Expand 10 before | Expand all | Expand 10 after
1265 } else if ((instr->Opc2Value() == 0x1) && (instr->Opc3Value() == 0x1)) { 1265 } else if ((instr->Opc2Value() == 0x1) && (instr->Opc3Value() == 0x1)) {
1266 // vneg 1266 // vneg
1267 Format(instr, "vneg'cond.f64 'Dd, 'Dm"); 1267 Format(instr, "vneg'cond.f64 'Dd, 'Dm");
1268 } else if ((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3)) { 1268 } else if ((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3)) {
1269 DecodeVCVTBetweenDoubleAndSingle(instr); 1269 DecodeVCVTBetweenDoubleAndSingle(instr);
1270 } else if ((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) { 1270 } else if ((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) {
1271 DecodeVCVTBetweenFloatingPointAndInteger(instr); 1271 DecodeVCVTBetweenFloatingPointAndInteger(instr);
1272 } else if ((instr->Opc2Value() == 0xA) && (instr->Opc3Value() == 0x3) && 1272 } else if ((instr->Opc2Value() == 0xA) && (instr->Opc3Value() == 0x3) &&
1273 (instr->Bit(8) == 1)) { 1273 (instr->Bit(8) == 1)) {
1274 // vcvt.f64.s32 Dd, Dd, #<fbits> 1274 // vcvt.f64.s32 Dd, Dd, #<fbits>
1275 int fraction_bits = 32 - ((instr->Bit(5) << 4) | instr->Bits(3, 0)); 1275 int fraction_bits = 32 - ((instr->Bits(3, 0) << 1) | instr->Bit(5));
1276 Format(instr, "vcvt'cond.f64.s32 'Dd, 'Dd"); 1276 Format(instr, "vcvt'cond.f64.s32 'Dd, 'Dd");
1277 out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_, 1277 out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
1278 ", #%d", fraction_bits); 1278 ", #%d", fraction_bits);
1279 } else if (((instr->Opc2Value() >> 1) == 0x6) && 1279 } else if (((instr->Opc2Value() >> 1) == 0x6) &&
1280 (instr->Opc3Value() & 0x1)) { 1280 (instr->Opc3Value() & 0x1)) {
1281 DecodeVCVTBetweenFloatingPointAndInteger(instr); 1281 DecodeVCVTBetweenFloatingPointAndInteger(instr);
1282 } else if (((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) && 1282 } else if (((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) &&
1283 (instr->Opc3Value() & 0x1)) { 1283 (instr->Opc3Value() & 0x1)) {
1284 DecodeVCMP(instr); 1284 DecodeVCMP(instr);
1285 } else if (((instr->Opc2Value() == 0x1)) && (instr->Opc3Value() == 0x3)) { 1285 } else if (((instr->Opc2Value() == 0x1)) && (instr->Opc3Value() == 0x3)) {
(...skipping 519 matching lines...) Expand 10 before | Expand all | Expand 10 after
1805 v8::internal::PrintF( 1805 v8::internal::PrintF(
1806 f, "%p %08x %s\n", 1806 f, "%p %08x %s\n",
1807 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); 1807 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
1808 } 1808 }
1809 } 1809 }
1810 1810
1811 1811
1812 } // namespace disasm 1812 } // namespace disasm
1813 1813
1814 #endif // V8_TARGET_ARCH_ARM 1814 #endif // V8_TARGET_ARCH_ARM
OLDNEW
« no previous file with comments | « src/arm/assembler-arm.cc ('k') | src/arm/simulator-arm.cc » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698