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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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2820 void Assembler::vcvt_f64_s32(const DwVfpRegister dst, | 2820 void Assembler::vcvt_f64_s32(const DwVfpRegister dst, |
2821 int fraction_bits, | 2821 int fraction_bits, |
2822 const Condition cond) { | 2822 const Condition cond) { |
2823 // Instruction details available in ARM DDI 0406C.b, A8-874. | 2823 // Instruction details available in ARM DDI 0406C.b, A8-874. |
2824 // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 1010(19-16) | Vd(15-12) | | 2824 // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 1010(19-16) | Vd(15-12) | |
2825 // 101(11-9) | sf=1(8) | sx=1(7) | 1(6) | i(5) | 0(4) | imm4(3-0) | 2825 // 101(11-9) | sf=1(8) | sx=1(7) | 1(6) | i(5) | 0(4) | imm4(3-0) |
2826 ASSERT(fraction_bits > 0 && fraction_bits <= 32); | 2826 ASSERT(fraction_bits > 0 && fraction_bits <= 32); |
2827 ASSERT(CpuFeatures::IsSupported(VFP3)); | 2827 ASSERT(CpuFeatures::IsSupported(VFP3)); |
2828 int vd, d; | 2828 int vd, d; |
2829 dst.split_code(&vd, &d); | 2829 dst.split_code(&vd, &d); |
2830 int i = ((32 - fraction_bits) >> 4) & 1; | 2830 int imm5 = 32 - fraction_bits; |
2831 int imm4 = (32 - fraction_bits) & 0xf; | 2831 int i = imm5 & 1; |
| 2832 int imm4 = (imm5 >> 1) & 0xf; |
2832 emit(cond | 0xE*B24 | B23 | d*B22 | 0x3*B20 | B19 | 0x2*B16 | | 2833 emit(cond | 0xE*B24 | B23 | d*B22 | 0x3*B20 | B19 | 0x2*B16 | |
2833 vd*B12 | 0x5*B9 | B8 | B7 | B6 | i*B5 | imm4); | 2834 vd*B12 | 0x5*B9 | B8 | B7 | B6 | i*B5 | imm4); |
2834 } | 2835 } |
2835 | 2836 |
2836 | 2837 |
2837 void Assembler::vneg(const DwVfpRegister dst, | 2838 void Assembler::vneg(const DwVfpRegister dst, |
2838 const DwVfpRegister src, | 2839 const DwVfpRegister src, |
2839 const Condition cond) { | 2840 const Condition cond) { |
2840 // Instruction details available in ARM DDI 0406C.b, A8-968. | 2841 // Instruction details available in ARM DDI 0406C.b, A8-968. |
2841 // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 0001(19-16) | Vd(15-12) | | 2842 // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 0001(19-16) | Vd(15-12) | |
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3732 ASSERT((index_64bit == count_of_64bit_) && | 3733 ASSERT((index_64bit == count_of_64bit_) && |
3733 (index_code_ptr == (index_64bit + count_of_code_ptr_)) && | 3734 (index_code_ptr == (index_64bit + count_of_code_ptr_)) && |
3734 (index_heap_ptr == (index_code_ptr + count_of_heap_ptr_)) && | 3735 (index_heap_ptr == (index_code_ptr + count_of_heap_ptr_)) && |
3735 (index_32bit == (index_heap_ptr + count_of_32bit_))); | 3736 (index_32bit == (index_heap_ptr + count_of_32bit_))); |
3736 } | 3737 } |
3737 | 3738 |
3738 | 3739 |
3739 } } // namespace v8::internal | 3740 } } // namespace v8::internal |
3740 | 3741 |
3741 #endif // V8_TARGET_ARCH_ARM | 3742 #endif // V8_TARGET_ARCH_ARM |
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