Optimize AOT's switchable calls for the monomorphic case.

runtime/vm/instructions_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM64.
 #if defined(TARGET_ARCH_ARM64)
 
 #include "vm/assembler.h"
 #include "vm/constants_arm64.h"
 #include "vm/cpu.h"
@@ skipping 341 matching lines @@
   movk3->SetMoveWideBits(MOVK, IP0, h3, 3, kDoubleWord);
   blr->SetUnconditionalBranchRegBits(BLR, IP0);
 
   ASSERT(kDeoptCallLengthInBytes == 5 * Instr::kInstrSize);
   CPU::FlushICache(pc, kDeoptCallLengthInBytes);
 }
 
 
 SwitchableCallPattern::SwitchableCallPattern(uword pc, const Code& code)
     : object_pool_(ObjectPool::Handle(code.GetObjectPool())),
-      cache_pool_index_(-1),
-      stub_pool_index_(-1) {
+      data_pool_index_(-1),
+      target_pool_index_(-1) {
   ASSERT(code.ContainsInstructionAt(pc));
-  // Last instruction: blr r1.
-  ASSERT(*(reinterpret_cast<uint32_t*>(pc) - 1) == 0xd63f0020);
+  // Last instruction: blr ip0.
+  ASSERT(*(reinterpret_cast<uint32_t*>(pc) - 1) == 0xd63f0200);
 
   Register reg;
   uword stub_load_end =
-      InstructionPattern::DecodeLoadWordFromPool(pc - 3 * Instr::kInstrSize,
+      InstructionPattern::DecodeLoadWordFromPool(pc - 2 * Instr::kInstrSize,
                                                  &reg,
-                                                 &stub_pool_index_);
+                                                 &target_pool_index_);
   ASSERT(reg == CODE_REG);
   InstructionPattern::DecodeLoadWordFromPool(stub_load_end,
                                              &reg,
-                                             &cache_pool_index_);
+                                             &data_pool_index_);
   ASSERT(reg == R5);
 }
 
 
-RawObject* SwitchableCallPattern::cache() const {
-  return reinterpret_cast<RawCode*>(
-      object_pool_.ObjectAt(cache_pool_index_));
+RawObject* SwitchableCallPattern::data() const {
+  return object_pool_.ObjectAt(data_pool_index_);
 }
 
 
-void SwitchableCallPattern::SetCache(const MegamorphicCache& cache) const {
-  ASSERT(Object::Handle(object_pool_.ObjectAt(cache_pool_index_)).IsICData());
-  object_pool_.SetObjectAt(cache_pool_index_, cache);
+RawCode* SwitchableCallPattern::target() const {
+  return reinterpret_cast<RawCode*>(
+      object_pool_.ObjectAt(target_pool_index_));
 }
 
 
-void SwitchableCallPattern::SetLookupStub(const Code& lookup_stub) const {
-  ASSERT(Object::Handle(object_pool_.ObjectAt(stub_pool_index_)).IsCode());
-  object_pool_.SetObjectAt(stub_pool_index_, lookup_stub);
+void SwitchableCallPattern::SetData(const Object& data) const {
+  ASSERT(!Object::Handle(object_pool_.ObjectAt(data_pool_index_)).IsCode());
+  object_pool_.SetObjectAt(data_pool_index_, data);
 }
 
 
+void SwitchableCallPattern::SetTarget(const Code& target) const {
+  ASSERT(Object::Handle(object_pool_.ObjectAt(target_pool_index_)).IsCode());
+  object_pool_.SetObjectAt(target_pool_index_, target);
+}
+
+
 ReturnPattern::ReturnPattern(uword pc)
     : pc_(pc) {
 }
 
 
 bool ReturnPattern::IsValid() const {
   Instr* bx_lr = Instr::At(pc_);
   const Register crn = ConcreteRegister(LR);
   const int32_t instruction = RET | (static_cast<int32_t>(crn) << kRnShift);
   return bx_lr->InstructionBits() == instruction;
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM64