Optimize AOT's switchable calls for the monomorphic case.

runtime/vm/assembler_x64.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // NOLINT
 #if defined(TARGET_ARCH_X64)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/heap.h"
@@ skipping 10 matching lines @@
 DECLARE_FLAG(bool, inline_alloc);
 
 
 Assembler::Assembler(bool use_far_branches)
     : buffer_(),
       prologue_offset_(-1),
       comments_(),
       constant_pool_allowed_(false) {
   // Far branching mode is only needed and implemented for MIPS and ARM.
   ASSERT(!use_far_branches);
+  MonomorphicCheckedEntry();
 }
 
 
 void Assembler::InitializeMemoryWithBreakpoints(uword data, intptr_t length) {
   memset(reinterpret_cast<void*>(data), Instr::kBreakPointInstruction, length);
 }
 
 
 void Assembler::call(Register reg) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
@@ skipping 3273 matching lines @@
 void Assembler::EnterStubFrame() {
   EnterDartFrame(0, kNoRegister);
 }
 
 
 void Assembler::LeaveStubFrame() {
   LeaveDartFrame();
 }
 
 
+void Assembler::NoMonomorphicCheckedEntry() {
+  buffer_.Reset();
+  for (intptr_t i = 0; i < Instructions::kCheckedEntryOffset; i++) {
+    int3();
+  }
+  ASSERT(CodeSize() == Instructions::kCheckedEntryOffset);
+}
+
+
+// RDI receiver, RBX guarded cid as Smi
+void Assembler::MonomorphicCheckedEntry() {
+  Label immediate, have_cid, miss;
+  Bind(&miss);
+  movq(CODE_REG, Address(THR, Thread::monomorphic_miss_stub_offset()));
+  movq(RCX, FieldAddress(CODE_REG, Code::entry_point_offset()));
+  jmp(RCX);
+
+  Bind(&immediate);
+  movq(R10, Immediate(kSmiCid));
+  jmp(&have_cid, kNearJump);
+
+  Comment("MonomorphicCheckedEntry");
+  ASSERT(CodeSize() == Instructions::kCheckedEntryOffset);
+  SmiUntag(RBX);
+  testq(RDI, Immediate(kSmiTagMask));
+  j(ZERO, &immediate, kNearJump);
+
+  LoadClassId(R10, RDI);
+
+  Bind(&have_cid);
+  cmpq(R10, RBX);
+  j(NOT_EQUAL, &miss, Assembler::kNearJump);
+
+  // Fall through to unchecked entry.
+  ASSERT(CodeSize() == Instructions::kUncheckedEntryOffset);
+  ASSERT((CodeSize() & kSmiTagMask) == kSmiTag);
+}
+
+
 #ifndef PRODUCT
 void Assembler::MaybeTraceAllocation(intptr_t cid,
                                      Label* trace,
                                      bool near_jump) {
   ASSERT(cid > 0);
   intptr_t state_offset = ClassTable::StateOffsetFor(cid);
   Register temp_reg = TMP;
   LoadIsolate(temp_reg);
   intptr_t table_offset =
       Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid);
@@ skipping 410 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfXmmRegisters));
   return xmm_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_X64