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Issue 2226893002: Optimize AOT's switchable calls for the monomorphic case. (Closed) Base URL: git@github.com:dart-lang/sdk.git@master
Patch Set: sync Created 4 years, 4 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" // NOLINT 5 #include "vm/globals.h" // NOLINT
6 #if defined(TARGET_ARCH_ARM) 6 #if defined(TARGET_ARCH_ARM)
7 7
8 #include "vm/assembler.h" 8 #include "vm/assembler.h"
9 #include "vm/cpu.h" 9 #include "vm/cpu.h"
10 #include "vm/longjump.h" 10 #include "vm/longjump.h"
(...skipping 3219 matching lines...) Expand 10 before | Expand all | Expand 10 after
3230 void Assembler::EnterStubFrame() { 3230 void Assembler::EnterStubFrame() {
3231 EnterDartFrame(0); 3231 EnterDartFrame(0);
3232 } 3232 }
3233 3233
3234 3234
3235 void Assembler::LeaveStubFrame() { 3235 void Assembler::LeaveStubFrame() {
3236 LeaveDartFrame(); 3236 LeaveDartFrame();
3237 } 3237 }
3238 3238
3239 3239
3240 void Assembler::NoMonomorphicCheckedEntry() {
3241 buffer_.Reset();
3242 bkpt(0);
3243 bkpt(0);
3244 bkpt(0);
3245 ASSERT(CodeSize() == Instructions::kCheckedEntryOffset);
3246 }
3247
3248
3249 // R0 receiver, R9 guarded cid as Smi
3250 void Assembler::MonomorphicCheckedEntry() {
3251 #if defined(TESTING) || defined(DEBUG)
3252 bool saved_use_far_branches = use_far_branches();
3253 set_use_far_branches(false);
3254 #endif
3255
3256 Label miss;
3257 Bind(&miss);
3258 ldr(CODE_REG, Address(THR, Thread::monomorphic_miss_stub_offset()));
3259 ldr(IP, FieldAddress(CODE_REG, Code::entry_point_offset()));
3260 bx(IP);
3261
3262 Comment("MonomorphicCheckedEntry");
3263 ASSERT(CodeSize() == Instructions::kCheckedEntryOffset);
3264 LoadClassIdMayBeSmi(R4, R0);
3265 SmiUntag(R9);
3266 cmp(R4, Operand(R9));
3267 b(&miss, NE);
3268
3269 // Fall through to unchecked entry.
3270 ASSERT(CodeSize() == Instructions::kUncheckedEntryOffset);
3271
3272 #if defined(TESTING) || defined(DEBUG)
3273 set_use_far_branches(saved_use_far_branches);
3274 #endif
3275 }
3276
3277
3240 #ifndef PRODUCT 3278 #ifndef PRODUCT
3241 void Assembler::MaybeTraceAllocation(intptr_t cid, 3279 void Assembler::MaybeTraceAllocation(intptr_t cid,
3242 Register temp_reg, 3280 Register temp_reg,
3243 Label* trace) { 3281 Label* trace) {
3244 LoadAllocationStatsAddress(temp_reg, cid); 3282 LoadAllocationStatsAddress(temp_reg, cid);
3245 const uword state_offset = ClassHeapStats::state_offset(); 3283 const uword state_offset = ClassHeapStats::state_offset();
3246 ldr(temp_reg, Address(temp_reg, state_offset)); 3284 ldr(temp_reg, Address(temp_reg, state_offset));
3247 tst(temp_reg, Operand(ClassHeapStats::TraceAllocationMask())); 3285 tst(temp_reg, Operand(ClassHeapStats::TraceAllocationMask()));
3248 b(trace, NE); 3286 b(trace, NE);
3249 } 3287 }
(...skipping 258 matching lines...) Expand 10 before | Expand all | Expand 10 after
3508 3546
3509 3547
3510 const char* Assembler::FpuRegisterName(FpuRegister reg) { 3548 const char* Assembler::FpuRegisterName(FpuRegister reg) {
3511 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); 3549 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
3512 return fpu_reg_names[reg]; 3550 return fpu_reg_names[reg];
3513 } 3551 }
3514 3552
3515 } // namespace dart 3553 } // namespace dart
3516 3554
3517 #endif // defined TARGET_ARCH_ARM 3555 #endif // defined TARGET_ARCH_ARM
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