Optimize AOT's switchable calls for the monomorphic case.

runtime/vm/assembler_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // NOLINT
 #if defined(TARGET_ARCH_ARM64)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/longjump.h"
@@ skipping 15 matching lines @@
 
 DEFINE_FLAG(bool, use_far_branches, false, "Always use far branches");
 
 
 Assembler::Assembler(bool use_far_branches)
     : buffer_(),
       prologue_offset_(-1),
       use_far_branches_(use_far_branches),
       comments_(),
       constant_pool_allowed_(false) {
+  MonomorphicCheckedEntry();
 }
 
 
 void Assembler::InitializeMemoryWithBreakpoints(uword data, intptr_t length) {
   ASSERT(Utils::IsAligned(data, 4));
   ASSERT(Utils::IsAligned(length, 4));
   const uword end = data + length;
   while (data < end) {
     *reinterpret_cast<int32_t*>(data) = Instr::kBreakPointInstruction;
     data += 4;
@@ skipping 1190 matching lines @@
 void Assembler::EnterStubFrame() {
   EnterDartFrame(0);
 }
 
 
 void Assembler::LeaveStubFrame() {
   LeaveDartFrame();
 }
 
 
+void Assembler::NoMonomorphicCheckedEntry() {
+  buffer_.Reset();
+  brk(0);
+  brk(0);
+  brk(0);
+  brk(0);
+  brk(0);
+  brk(0);
+  ASSERT(CodeSize() == Instructions::kCheckedEntryOffset);
+}
+
+
+// R0 receiver, R5 guarded cid as Smi
+void Assembler::MonomorphicCheckedEntry() {
+  bool saved_use_far_branches = use_far_branches();
+  set_use_far_branches(false);
+
+  Label immediate, have_cid, miss;
+  Bind(&miss);
+  ldr(CODE_REG, Address(THR, Thread::monomorphic_miss_stub_offset()));
+  ldr(IP0, FieldAddress(CODE_REG, Code::entry_point_offset()));
+  br(IP0);
+  brk(0);
+
+  Bind(&immediate);
+  movz(R1, Immediate(kSmiCid), 0);
+  b(&have_cid);
+
+  Comment("MonomorphicCheckedEntry");
+  ASSERT(CodeSize() == Instructions::kCheckedEntryOffset);
+  tsti(R0, Immediate(kSmiTagMask));
+  SmiUntag(R5);
+  b(&immediate, EQ);
+
+  LoadClassId(R1, R0);
+
+  Bind(&have_cid);
+  cmp(R1, Operand(R5));
+  b(&miss, NE);
+
+  // Fall through to unchecked entry.
+  ASSERT(CodeSize() == Instructions::kUncheckedEntryOffset);
+
+  set_use_far_branches(saved_use_far_branches);
+}
+
+
 #ifndef PRODUCT
 void Assembler::MaybeTraceAllocation(intptr_t cid,
                                      Register temp_reg,
                                      Label* trace) {
   ASSERT(cid > 0);
   intptr_t state_offset = ClassTable::StateOffsetFor(cid);
   LoadIsolate(temp_reg);
   intptr_t table_offset =
       Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid);
   ldr(temp_reg, Address(temp_reg, table_offset));
@@ skipping 172 matching lines @@
     add(base, array, Operand(index, LSL, shift));
   }
   const OperandSize size = Address::OperandSizeFor(cid);
   ASSERT(Address::CanHoldOffset(offset, Address::Offset, size));
   return Address(base, offset, Address::Offset, size);
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM64