MIPS: Implement Bovc and Bnvc instruction macros.

src/mips/macro-assembler-mips.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <limits.h>  // For LONG_MIN, LONG_MAX.
 
 #if V8_TARGET_ARCH_MIPS
 
 #include "src/base/bits.h"
 #include "src/base/division-by-constant.h"
@@ skipping 1168 matching lines @@
   if (IsMipsArchVariant(kMips32r6) && sa <= 4) {
     lsa(rd, rt, rs, sa - 1);
   } else {
     Register tmp = rd.is(rt) ? scratch : rd;
     DCHECK(!tmp.is(rt));
     sll(tmp, rs, sa);
     Addu(rd, rt, tmp);
   }
 }
 
+void MacroAssembler::Bovc(Register rs, Register rt, Label* L) {
+  if (is_trampoline_emitted()) {
+    Label skip;
+    bnvc(rs, rt, &skip);
+    BranchLong(L, PROTECT);
+    bind(&skip);
+  } else {
+    bovc(rs, rt, L);
+  }
+}
+
+void MacroAssembler::Bnvc(Register rs, Register rt, Label* L) {
+  if (is_trampoline_emitted()) {
+    Label skip;
+    bovc(rs, rt, &skip);
+    BranchLong(L, PROTECT);
+    bind(&skip);
+  } else {
+    bnvc(rs, rt, L);
+  }
+}
 
 // ------------Pseudo-instructions-------------
 
 // Word Swap Byte
 void MacroAssembler::ByteSwapSigned(Register reg, int operand_size) {
   DCHECK(operand_size == 1 || operand_size == 2 || operand_size == 4);
   if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) {
     if (operand_size == 2) {
       seh(reg, reg);
     } else if (operand_size == 1) {
@@ skipping 2131 matching lines @@
     nop();
 
   return true;
 }
 
 
 bool MacroAssembler::BranchShortCheck(int32_t offset, Label* L, Condition cond,
                                       Register rs, const Operand& rt,
                                       BranchDelaySlot bdslot) {
   BRANCH_ARGS_CHECK(cond, rs, rt);
-
   if (!L) {
     if (IsMipsArchVariant(kMips32r6) && bdslot == PROTECT) {
       DCHECK(is_int26(offset));
       return BranchShortHelperR6(offset, nullptr, cond, rs, rt);
     } else {
       DCHECK(is_int16(offset));
       return BranchShortHelper(offset, nullptr, cond, rs, rt, bdslot);
     }
   } else {
     DCHECK(offset == 0);
@@ skipping 2036 matching lines @@
     if (!overflow_label) {
       DCHECK(no_overflow_label);
       DCHECK(!dst.is(scratch));
       Register left_reg = left.is(dst) ? scratch : left;
       Register right_reg = right.is(dst) ? t9 : right;
       DCHECK(!dst.is(left_reg));
       DCHECK(!dst.is(right_reg));
       Move(left_reg, left);
       Move(right_reg, right);
       addu(dst, left, right);
-      bnvc(left_reg, right_reg, no_overflow_label);
+      Bnvc(left_reg, right_reg, no_overflow_label);
     } else {
-      bovc(left, right, overflow_label);
+      Bovc(left, right, overflow_label);
       addu(dst, left, right);
       if (no_overflow_label) bc(no_overflow_label);
     }
   } else {
     Register overflow_dst = t9;
     DCHECK(!dst.is(scratch));
     DCHECK(!dst.is(overflow_dst));
     DCHECK(!scratch.is(overflow_dst));
     DCHECK(!left.is(overflow_dst));
     DCHECK(!right.is(overflow_dst));
@@ skipping 1499 matching lines @@
   if (mag.shift > 0) sra(result, result, mag.shift);
   srl(at, dividend, 31);
   Addu(result, result, Operand(at));
 }
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_MIPS