ARM64: Introduce a version of ADR handling distant targets.

src/arm64/instructions-arm64.h

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 142 matching lines @@
   }
 
   #define DEFINE_GETTER(Name, HighBit, LowBit, Func)             \
   int64_t Name() const { return Func(HighBit, LowBit); }
   INSTRUCTION_FIELDS_LIST(DEFINE_GETTER)
   #undef DEFINE_GETTER
 
   // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST),
   // formed from ImmPCRelLo and ImmPCRelHi.
   int ImmPCRel() const {
+    ASSERT(IsPCRelAddressing());
     int const offset = ((ImmPCRelHi() << ImmPCRelLo_width) | ImmPCRelLo());
     int const width = ImmPCRelLo_width + ImmPCRelHi_width;
-    return signed_bitextract_32(width-1, 0, offset);
+    return signed_bitextract_32(width - 1, 0, offset);
   }
 
   uint64_t ImmLogical();
   float ImmFP32();
   double ImmFP64();
 
   LSDataSize SizeLSPair() const {
     return CalcLSPairDataSize(
         static_cast<LoadStorePairOp>(Mask(LoadStorePairMask)));
   }
@@ skipping 20 matching lines @@
   }
 
   bool IsLdrLiteralX() const {
     return Mask(LoadLiteralMask) == LDR_x_lit;
   }
 
   bool IsPCRelAddressing() const {
     return Mask(PCRelAddressingFMask) == PCRelAddressingFixed;
   }
 
+  bool IsAdr() const {
+    return Mask(PCRelAddressingMask) == ADR;
+  }
+
   bool IsLogicalImmediate() const {
     return Mask(LogicalImmediateFMask) == LogicalImmediateFixed;
   }
 
   bool IsAddSubImmediate() const {
     return Mask(AddSubImmediateFMask) == AddSubImmediateFixed;
   }
 
+  bool IsAddSubShifted() const {
+    return Mask(AddSubShiftedFMask) == AddSubShiftedFixed;
+  }
+
   bool IsAddSubExtended() const {
     return Mask(AddSubExtendedFMask) == AddSubExtendedFixed;
   }
 
   // Match any loads or stores, including pairs.
   bool IsLoadOrStore() const {
     return Mask(LoadStoreAnyFMask) == LoadStoreAnyFixed;
   }
 
   // Match any loads, including pairs.
@@ skipping 156 matching lines @@
 
   template<typename T> V8_INLINE static Instruction* Cast(T src) {
     return reinterpret_cast<Instruction*>(src);
   }
 
   V8_INLINE ptrdiff_t DistanceTo(Instruction* target) {
     return reinterpret_cast<Address>(target) - reinterpret_cast<Address>(this);
   }
 
 
+  static const int ImmPCRelRangeBitwidth = 21;
+  static bool IsValidPCRelOffset(int offset) {
+    return is_int21(offset);
+  }
   void SetPCRelImmTarget(Instruction* target);
   void SetBranchImmTarget(Instruction* target);
 };
 
 
 // Where Instruction looks at instructions generated by the Assembler,
 // InstructionSequence looks at instructions sequences generated by the
 // MacroAssembler.
 class InstructionSequence : public Instruction {
  public:
@@ skipping 92 matching lines @@
   TRACE_ENABLE   = 1 << 6,
   TRACE_DISABLE  = 2 << 6,
   TRACE_OVERRIDE = 3 << 6
 };
 
 
 } }  // namespace v8::internal
 
 
 #endif  // V8_ARM64_INSTRUCTIONS_ARM64_H_