ARM: Avoid VMSR instruction when converting to clamped uint8

src/arm/disasm-arm.cc

Index: src/arm/disasm-arm.cc
diff --git a/src/arm/disasm-arm.cc b/src/arm/disasm-arm.cc
index aa8ee22b73a3c4e7b92ea3312e7bd5b3da8bf96a..9faf91ac4b29c770c0739578def4d0248df70238 100644
--- a/src/arm/disasm-arm.cc
+++ b/src/arm/disasm-arm.cc
@@ -138,6 +138,7 @@ class Decoder {
   void DecodeVCMP(Instruction* instr);
   void DecodeVCVTBetweenDoubleAndSingle(Instruction* instr);
   void DecodeVCVTBetweenFloatingPointAndInteger(Instruction* instr);
+  void DecodeVCVTBetweenFloatingPointAndFixedPoint(Instruction* instr);
 
   const disasm::NameConverter& converter_;
   Vector<char> out_buffer_;
@@ -1233,6 +1234,7 @@ int Decoder::DecodeType7(Instruction* instr) {
 // vcvt: Dd = Sm
 // vcvt: Sd = Dm
 // vcvt.f64.s32 Dd, Dd, #<fbits>
+// vcvt.u32.f64 Dd, Dd, #<fbits>
 // Dd = vabs(Dm)
 // Dd = vneg(Dm)
 // Dd = vadd(Dn, Dm)
@@ -1269,13 +1271,10 @@ void Decoder::DecodeTypeVFP(Instruction* instr) {
         DecodeVCVTBetweenDoubleAndSingle(instr);
       } else if ((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) {
         DecodeVCVTBetweenFloatingPointAndInteger(instr);
-      } else if ((instr->Opc2Value() == 0xA) && (instr->Opc3Value() == 0x3) &&
-                 (instr->Bit(8) == 1)) {
-        // vcvt.f64.s32 Dd, Dd, #<fbits>
-        int fraction_bits = 32 - ((instr->Bit(5) << 4) | instr->Bits(3, 0));
-        Format(instr, "vcvt'cond.f64.s32 'Dd, 'Dd");
-        out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
-                                        ", #%d", fraction_bits);
+      } else if ((instr->Opc2Value() & 0x2) && (instr->Opc2Value() & 0x8) &&
+                 (instr->Opc3Value() == 0x3) &&
+                 (instr->Bit(5) || instr->Bits(3, 0))) {
+        DecodeVCVTBetweenFloatingPointAndFixedPoint(instr);
       } else if (((instr->Opc2Value() >> 1) == 0x6) &&
                  (instr->Opc3Value() & 0x1)) {
         DecodeVCVTBetweenFloatingPointAndInteger(instr);
@@ -1466,6 +1465,55 @@ void Decoder::DecodeVCVTBetweenFloatingPointAndInteger(Instruction* instr) {
 }
 
 
+void Decoder::DecodeVCVTBetweenFloatingPointAndFixedPoint(Instruction* instr) {
+  VERIFY((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
+  VERIFY((instr->Opc2Value() & 0x2) && (instr->Opc2Value() & 0x8));
+  VERIFY(instr->Opc3Value() == 0x3);
+  VERIFY(instr->Bit(5) || instr->Bits(3, 0));
+
+  bool to_integer = (instr->Bit(18) == 1);
+  bool dp_operation = (instr->SzValue() == 1);
+  bool unsigned_integer = (instr->Bit(16) == 1);
+
+  int sx = instr->Bit(7);
+
+  int fraction_bits = (sx ? 32 : 16) -
+                      ((instr->Bits(3, 0) << 1) | instr->Bit(5));
+
+  if (to_integer) {
+    if (dp_operation) {
+      if (unsigned_integer) {
+        Format(instr, "vcvt'cond.u32.f64 'Dd, 'Dd");
+      } else {
+        Format(instr, "vcvt'cond.s32.f64 'Dd, 'Dd");
+      }
+    } else {
+      if (unsigned_integer) {
+        Format(instr, "vcvt'cond.u32.f32 'Sd, 'Sd");
+      } else {
+        Format(instr, "vcvt'cond.s32.f32 'Sd, 'Sd");
+      }
+    }
+  } else {
+    if (dp_operation) {
+      if (unsigned_integer) {
+        Format(instr, "vcvt'cond.f64.u32 'Dd, 'Dd");
+      } else {
+        Format(instr, "vcvt'cond.f64.s32 'Dd, 'Dd");
+      }
+    } else {
+      if (unsigned_integer) {
+        Format(instr, "vcvt'cond.f32.u32 'Sd, 'Sd");
+      } else {
+        Format(instr, "vcvt'cond.f32.s32 'Sd, 'Sd");
+      }
+    }
+  }
+  out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                                  ", #%d", fraction_bits);
+}
+
+
 // Decode Type 6 coprocessor instructions.
 // Dm = vmov(Rt, Rt2)
 // <Rt, Rt2> = vmov(Dm)