ARM: Avoid VMSR instruction when converting to clamped uint8

src/arm/assembler-arm.cc

Index: src/arm/assembler-arm.cc
diff --git a/src/arm/assembler-arm.cc b/src/arm/assembler-arm.cc
index 297cdcc0395819eda41599aad5f138b4671177b2..6b07753457d89600b3a6e8ca867c9503e5d1e86d 100644
--- a/src/arm/assembler-arm.cc
+++ b/src/arm/assembler-arm.cc
@@ -2761,6 +2761,43 @@ static Instr EncodeVCVT(const VFPType dst_type,
 }
 
 
+static Instr EncodeVCVTFraction(const VFPType dst_type,
+                                const int dst_src_code,
+                                const VFPType src_type,
+                                const int fraction_bits,
+                                const Condition cond) {
+  // Conversion between IEEE floating point and 32-bit fixed point.
+  // Instruction details available in ARM DDI 0406C.b, A8-874.
+  // cond(31-28) | 11101(27-23) | D(22) | 111(21-19) | op(18) | 1(17) | U(16) |
+  // Vd(15-12) | 101(11-9) | sf(8) | sx(7) | 1(6) | i(5) | 0(4) | imm4(3-0)
+  ASSERT(fraction_bits > 0 && fraction_bits <= 32);
+  ASSERT(CpuFeatures::IsSupported(VFP3));
+  ASSERT(IsIntegerVFPType(dst_type) != IsIntegerVFPType(src_type));
+  int D, Vd, U, sz, op;
+  if (IsIntegerVFPType(dst_type)) {
+    // Wider register should be set to Vd, D
+    SplitRegCode(src_type, dst_src_code, &Vd, &D);
+    U = IsSignedVFPType(dst_type) ? 0x0 : 0x1;
+    sz = IsDoubleVFPType(src_type) ? 0x1 : 0x0;
+    op = 0x1;
+  } else {
+    SplitRegCode(dst_type, dst_src_code, &Vd, &D);
+    U = IsSignedVFPType(src_type) ? 0x0 : 0x1;
+    sz = IsDoubleVFPType(dst_type) ? 0x1 : 0x0;
+    op = 0x0;
+  }
+  int sx = 0x1;
+  int imm5 = (sx ? 32 : 16) - fraction_bits;
+  ASSERT(imm5 >= 0);
+  // Encode imm5
+  int i = imm5 & 1;
+  int imm4 = imm5 >> 1;
+
+  return (cond | 0xE*B24 | B23 | D*B22 | 0x3*B20 | B19 | op*B18 | B17 | U*B16 |
+          Vd*B12 | 0x5*B9 | sz*B8 | sx*B7 | B6 | i*B5 | imm4);
+}
+
+
 void Assembler::vcvt_f64_s32(const DwVfpRegister dst,
                              const SwVfpRegister src,
                              VFPConversionMode mode,
@@ -2818,19 +2855,16 @@ void Assembler::vcvt_f32_f64(const SwVfpRegister dst,
 
 
 void Assembler::vcvt_f64_s32(const DwVfpRegister dst,
-                             int fraction_bits,
+                             const int fraction_bits,
                              const Condition cond) {
-  // Instruction details available in ARM DDI 0406C.b, A8-874.
-  // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 1010(19-16) | Vd(15-12) |
-  // 101(11-9) | sf=1(8) | sx=1(7) | 1(6) | i(5) | 0(4) | imm4(3-0)
-  ASSERT(fraction_bits > 0 && fraction_bits <= 32);
-  ASSERT(CpuFeatures::IsSupported(VFP3));
-  int vd, d;
-  dst.split_code(&vd, &d);
-  int i = ((32 - fraction_bits) >> 4) & 1;
-  int imm4 = (32 - fraction_bits) & 0xf;
-  emit(cond | 0xE*B24 | B23 | d*B22 | 0x3*B20 | B19 | 0x2*B16 |
-       vd*B12 | 0x5*B9 | B8 | B7 | B6 | i*B5 | imm4);
+  emit(EncodeVCVTFraction(F64, dst.code(), S32, fraction_bits, cond));
+}
+
+
+void Assembler::vcvt_u32_f64(const DwVfpRegister dst,
+                             const int fraction_bits,
+                             const Condition cond) {
+  emit(EncodeVCVTFraction(U32, dst.code(), F64, fraction_bits, cond));
 }