ARM: Avoid VMSR instruction when converting to clamped uint8

test/cctest/test-disasm-arm.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 574 matching lines @@
     COMPARE(vcvt_u32_f64(s0, d0),
             "eebc0bc0       vcvt.u32.f64 s0, d0");
     COMPARE(vcvt_s32_f64(s0, d0),
             "eebd0bc0       vcvt.s32.f64 s0, d0");
     COMPARE(vcvt_f64_u32(d0, s1),
             "eeb80b60       vcvt.f64.u32 d0, s1");
     COMPARE(vcvt_f64_s32(d0, s1),
             "eeb80be0       vcvt.f64.s32 d0, s1");
     COMPARE(vcvt_f32_s32(s0, s2),
             "eeb80ac1       vcvt.f32.s32 s0, s2");
-    COMPARE(vcvt_f64_s32(d0, 1),
-            "eeba0bef       vcvt.f64.s32 d0, d0, #1");
+    if (CpuFeatures::IsSupported(VFP3)) {
+      COMPARE(vcvt_f64_s32(d0, 1),
+              "eeba0bef       vcvt.f64.s32 d0, d0, #1");
+      COMPARE(vcvt_u32_f64(d0, 24),
+              "eebf0bc4       vcvt.u32.f64 d0, d0, #24");
+    }
 
     if (CpuFeatures::IsSupported(VFP32DREGS)) {
       COMPARE(vmov(d3, d27),
               "eeb03b6b       vmov.f64 d3, d27");
       COMPARE(vmov(d18, d7),
               "eef02b47       vmov.f64 d18, d7");
       COMPARE(vmov(d18, r2, r3),
               "ec432b32       vmov d18, r2, r3");
       COMPARE(vmov(r2, r3, d18),
               "ec532b32       vmov r2, r3, d18");
@@ skipping 290 matching lines @@
             "e16dc7ff       strd ip, [sp, #-127]!");
 
     COMPARE(pld(MemOperand(r1, 0)),
             "f5d1f000       pld [r1]");
     COMPARE(pld(MemOperand(r2, 128)),
             "f5d2f080       pld [r2, #+128]");
   }
 
   VERIFY_RUN();
 }