ARM: Avoid VMSR instruction when converting to clamped uint8

src/arm/assembler-arm.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 2743 matching lines @@
     // Instruction details available in ARM DDI 0406B, A8.6.298.
     // cond(31-28) | 11101(27-23)| D(22) | 11(21-20) | 0111(19-16) |
     // Vd(15-12) | 101(11-9) | sz(8) | 1(7) | 1(6) | M(5) | 0(4) | Vm(3-0)
     int sz = IsDoubleVFPType(src_type) ? 0x1 : 0x0;
     return (cond | 0xE*B24 | B23 | D*B22 | 0x3*B20 | 0x7*B16 |
             Vd*B12 | 0x5*B9 | sz*B8 | B7 | B6 | M*B5 | Vm);
   }
 }
 
 
+static Instr EncodeVCVTFraction(const VFPType dst_type,
+                                const int dst_src_code,
+                                const VFPType src_type,
+                                const int fraction_bits,
+                                const Condition cond) {
+  // Conversion between IEEE floating point and 32-bit fixed point.
+  // Instruction details available in ARM DDI 0406C.b, A8-874.
+  // cond(31-28) | 11101(27-23) | D(22) | 111(21-19) | op(18) | 1(17) | U(16) |
+  // Vd(15-12) | 101(11-9) | sf(8) | sx(7) | 1(6) | i(5) | 0(4) | imm4(3-0)
+  ASSERT(fraction_bits > 0 && fraction_bits <= 32);
+  ASSERT(CpuFeatures::IsSupported(VFP3));
+  ASSERT(IsIntegerVFPType(dst_type) != IsIntegerVFPType(src_type));
+  int D, Vd, U, sz, op;
+  if (IsIntegerVFPType(dst_type)) {
+    // Wider register should be set to Vd, D
+    SplitRegCode(src_type, dst_src_code, &Vd, &D);
+    U = IsSignedVFPType(dst_type) ? 0x0 : 0x1;
+    sz = IsDoubleVFPType(src_type) ? 0x1 : 0x0;
+    op = 0x1;
+  } else {
+    SplitRegCode(dst_type, dst_src_code, &Vd, &D);
+    U = IsSignedVFPType(src_type) ? 0x0 : 0x1;
+    sz = IsDoubleVFPType(dst_type) ? 0x1 : 0x0;
+    op = 0x0;
+  }
+  int sx = 0x1;
+  int imm5 = (sx ? 32 : 16) - fraction_bits;
+  ASSERT(imm5 >= 0);
+  // Encode imm5
+  int i = imm5 & 1;
+  int imm4 = imm5 >> 1;
+
+  return (cond | 0xE*B24 | B23 | D*B22 | 0x3*B20 | B19 | op*B18 | B17 | U*B16 |
+          Vd*B12 | 0x5*B9 | sz*B8 | sx*B7 | B6 | i*B5 | imm4);
+}
+
+
 void Assembler::vcvt_f64_s32(const DwVfpRegister dst,
                              const SwVfpRegister src,
                              VFPConversionMode mode,
                              const Condition cond) {
   emit(EncodeVCVT(F64, dst.code(), S32, src.code(), mode, cond));
 }
 
 
 void Assembler::vcvt_f32_s32(const SwVfpRegister dst,
                              const SwVfpRegister src,
@@ skipping 37 matching lines @@
 
 void Assembler::vcvt_f32_f64(const SwVfpRegister dst,
                              const DwVfpRegister src,
                              VFPConversionMode mode,
                              const Condition cond) {
   emit(EncodeVCVT(F32, dst.code(), F64, src.code(), mode, cond));
 }
 
 
 void Assembler::vcvt_f64_s32(const DwVfpRegister dst,
-                             int fraction_bits,
+                             const int fraction_bits,
                              const Condition cond) {
-  // Instruction details available in ARM DDI 0406C.b, A8-874.
-  // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 1010(19-16) | Vd(15-12) |
-  // 101(11-9) | sf=1(8) | sx=1(7) | 1(6) | i(5) | 0(4) | imm4(3-0)
-  ASSERT(fraction_bits > 0 && fraction_bits <= 32);
-  ASSERT(CpuFeatures::IsSupported(VFP3));
-  int vd, d;
-  dst.split_code(&vd, &d);
-  int i = ((32 - fraction_bits) >> 4) & 1;
-  int imm4 = (32 - fraction_bits) & 0xf;
-  emit(cond | 0xE*B24 | B23 | d*B22 | 0x3*B20 | B19 | 0x2*B16 |
-       vd*B12 | 0x5*B9 | B8 | B7 | B6 | i*B5 | imm4);
+  emit(EncodeVCVTFraction(F64, dst.code(), S32, fraction_bits, cond));
 }
 
 
+void Assembler::vcvt_u32_f64(const DwVfpRegister dst,
+                             const int fraction_bits,
+                             const Condition cond) {
+  emit(EncodeVCVTFraction(U32, dst.code(), F64, fraction_bits, cond));
+}
+
+
 void Assembler::vneg(const DwVfpRegister dst,
                      const DwVfpRegister src,
                      const Condition cond) {
   // Instruction details available in ARM DDI 0406C.b, A8-968.
   // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 0001(19-16) | Vd(15-12) |
   // 101(11-9) | sz=1(8) | 0(7) | 1(6) | M(5) | 0(4) | Vm(3-0)
   int vd, d;
   dst.split_code(&vd, &d);
   int vm, m;
   src.split_code(&vm, &m);
@@ skipping 885 matching lines @@
   ASSERT((index_64bit == count_of_64bit_) &&
          (index_code_ptr == (index_64bit + count_of_code_ptr_)) &&
          (index_heap_ptr == (index_code_ptr + count_of_heap_ptr_)) &&
          (index_32bit == (index_heap_ptr + count_of_32bit_)));
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM