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Issue 22240002: Rework PNaCl memory ordering (Closed) Base URL: http://git.chromium.org/native_client/pnacl-llvm.git@master
Patch Set: Created 7 years, 4 months ago
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1 ============================== 1 ==============================
2 PNaCl Bitcode Reference Manual 2 PNaCl Bitcode Reference Manual
3 ============================== 3 ==============================
4 4
5 .. contents:: 5 .. contents::
6 :local: 6 :local:
7 :depth: 3 7 :depth: 3
8 8
9 Introduction 9 Introduction
10 ============ 10 ============
(...skipping 125 matching lines...) Expand 10 before | Expand all | Expand 10 after
136 136
137 `LLVM LangRef: Module-Level Inline Assembly <LangRef.html#moduleasm>`_ 137 `LLVM LangRef: Module-Level Inline Assembly <LangRef.html#moduleasm>`_
138 138
139 PNaCl bitcode does not support inline assembly. 139 PNaCl bitcode does not support inline assembly.
140 140
141 Volatile Memory Accesses 141 Volatile Memory Accesses
142 ------------------------ 142 ------------------------
143 143
144 `LLVM LangRef: Volatile Memory Accesses <LangRef.html#volatile>`_ 144 `LLVM LangRef: Volatile Memory Accesses <LangRef.html#volatile>`_
145 145
146 PNaCl bitcode does not support volatile memory accesses. The ``volatile`` 146 PNaCl bitcode does not support volatile memory accesses. The
147 attribute on loads and stores is not supported. See the 147 ``volatile`` attribute on loads and stores is not supported. See the
148 `PNaCl Developer's Guide <PNaClDeveloperGuide.html>`_ for more details. 148 `PNaCl Developer's Guide <PNaClDeveloperGuide.html>`_ for more details.
149 149
150 Memory Model for Concurrent Operations 150 Memory Model for Concurrent Operations
151 -------------------------------------- 151 --------------------------------------
152 152
153 `LLVM LangRef: Memory Model for Concurrent Operations <LangRef.html#memmodel>`_ 153 `LLVM LangRef: Memory Model for Concurrent Operations
154 <LangRef.html#memmodel>`_
154 155
155 See the `PNaCl Developer's Guide <PNaClDeveloperGuide.html>`_ for more details. 156 See the `PNaCl Developer's Guide <PNaClDeveloperGuide.html>`_ for more
157 details.
156 158
157 Atomic Memory Ordering Constraints 159 Atomic Memory Ordering Constraints
158 ---------------------------------- 160 ----------------------------------
159 161
160 `LLVM LangRef: Atomic Memory Ordering Constraints <LangRef.html#ordering>`_ 162 `LLVM LangRef: Atomic Memory Ordering Constraints <LangRef.html#ordering>`_
161 163
162 PNaCl bitcode currently supports sequential consistency only, through its 164 PNaCl bitcode currently supports sequential consistency only, through
163 `atomic intrinsics`_. See the 165 its `atomic intrinsics`_. See the `PNaCl Developer's Guide
164 `PNaCl Developer's Guide <PNaClDeveloperGuide.html>`_ for more details. 166 <PNaClDeveloperGuide.html>`_ for more details. It supports the usually
eliben 2013/08/05 18:35:54 Parse error on: "the usually C11/C++11 sequential
JF 2013/08/05 20:37:48 Done.
167 C11/C++11 sequential consistency, as well as a stronger form of
168 sequential consistency which attempts to act as a barrier for non-atomic
169 and non-``volatile`` accesses.
165 170
166 Fast-Math Flags 171 Fast-Math Flags
167 --------------- 172 ---------------
168 173
169 `LLVM LangRef: Fast-Math Flags <LangRef.html#fastmath>`_ 174 `LLVM LangRef: Fast-Math Flags <LangRef.html#fastmath>`_
170 175
171 Fast-math mode is not currently supported by the PNaCl bitcode. 176 Fast-math mode is not currently supported by the PNaCl bitcode.
172 177
173 Type System 178 Type System
174 =========== 179 ===========
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403 408
404 See :ref:`Setjmp and Longjmp <setjmplongjmp>`. 409 See :ref:`Setjmp and Longjmp <setjmplongjmp>`.
405 410
406 .. _atomic intrinsics: 411 .. _atomic intrinsics:
407 412
408 * ``llvm.nacl.atomic.store`` 413 * ``llvm.nacl.atomic.store``
409 * ``llvm.nacl.atomic.load`` 414 * ``llvm.nacl.atomic.load``
410 * ``llvm.nacl.atomic.rmw`` 415 * ``llvm.nacl.atomic.rmw``
411 * ``llvm.nacl.atomic.cmpxchg`` 416 * ``llvm.nacl.atomic.cmpxchg``
412 * ``llvm.nacl.atomic.fence`` 417 * ``llvm.nacl.atomic.fence``
418 * ``llvm.nacl.atomic.is.lock.free``
413 419
414 See :ref:`atomic intrinsics <atomicintrinsics>`. 420 See :ref:`atomic intrinsics <atomicintrinsics>`.
415 421
416 .. _threadpointerintrinsics: 422 .. _threadpointerintrinsics:
417 423
418 Thread pointer related intrinsics 424 Thread pointer related intrinsics
419 --------------------------------- 425 ---------------------------------
420 426
421 .. code-block:: llvm 427 .. code-block:: llvm
422 428
423 declare i8* @llvm.nacl.read.tp() 429 declare i8* @llvm.nacl.read.tp()
424 430
425 Returns the thread pointer, which can be set by the embedding sandbox's runtime. 431 Returns the thread pointer, which can be set by the embedding sandbox's runtime.
426 432
427 .. _setjmplongjmp: 433 .. _setjmplongjmp:
428 434
429 Setjmp and Longjmp 435 Setjmp and Longjmp
430 ------------------ 436 ------------------
431 437
432 .. code-block:: llvm 438 .. code-block:: llvm
433 439
434 declare void @llvm.nacl.longjmp(i8* %jmpbuf, i32) 440 declare void @llvm.nacl.longjmp(i8* %jmpbuf, i32)
435 declare i32 @llvm.nacl.setjmp(i8* %jmpbuf) 441 declare i32 @llvm.nacl.setjmp(i8* %jmpbuf)
436 442
437 These intrinsics implement the semantics of C11 ``setjmp`` and ``longjmp``. The 443 These intrinsics implement the semantics of C11 ``setjmp`` and
eliben 2013/08/05 18:35:54 What are these reformatting changes doing here?
JF 2013/08/05 20:37:48 Enthusiastic select-and-auto-format got a bit furt
438 ``jmpbuf`` pointer must be 64-bit aligned and point to at least 1024 bytes of 444 ``longjmp``. The ``jmpbuf`` pointer must be 64-bit aligned and point to
439 allocated memory. 445 at least 1024 bytes of allocated memory.
440 446
441 .. _atomicintrinsics: 447 .. _atomicintrinsics:
442 448
443 Atomic intrinsics 449 Atomic intrinsics
444 ----------------- 450 -----------------
445 451
446 .. code-block:: llvm 452 .. code-block:: llvm
447 453
448 declare iN @llvm.nacl.atomic.load.<size>( 454 declare iN @llvm.nacl.atomic.load.<size>(
449 iN* <source>, i32 <memory_order>) 455 iN* <source>, i32 <memory_order>)
450 declare void @llvm.nacl.atomic.store.<size>( 456 declare void @llvm.nacl.atomic.store.<size>(
451 iN <operand>, iN* <destination>, i32 <memory_order>) 457 iN <operand>, iN* <destination>, i32 <memory_order>)
452 declare iN @llvm.nacl.atomic.rmw.<size>( 458 declare iN @llvm.nacl.atomic.rmw.<size>(
453 i32 <computation>, iN* <object>, iN <operand>, i32 <memory_order>) 459 i32 <computation>, iN* <object>, iN <operand>, i32 <memory_order>)
454 declare iN @llvm.nacl.atomic.cmpxchg.<size>( 460 declare iN @llvm.nacl.atomic.cmpxchg.<size>(
455 iN* <object>, iN <expected>, iN <desired>, 461 iN* <object>, iN <expected>, iN <desired>,
456 i32 <memory_order_success>, i32 <memory_order_failure>) 462 i32 <memory_order_success>, i32 <memory_order_failure>)
457 declare void @llvm.nacl.atomic.fence(i32 <memory_order>) 463 declare void @llvm.nacl.atomic.fence(i32 <memory_order>)
458 464
459 Each of these intrinsics is overloaded on the ``iN`` argument, which 465 Each of these intrinsics is overloaded on the ``iN`` argument, which is
460 is reflected through ``<size>`` in the overload's name. Integral types 466 reflected through ``<size>`` in the overload's name. Integral types of
461 of 8, 16, 32 and 64-bit width are supported for these arguments. 467 8, 16, 32 and 64-bit width are supported for these arguments.
462 468
463 The ``@llvm.nacl.atomic.rmw`` intrinsic implements the following 469 The ``@llvm.nacl.atomic.rmw`` intrinsic implements the following
464 read-modify-write operations, from the general and arithmetic sections 470 read-modify-write operations, from the general and arithmetic sections
465 of the C11/C++11 standards: 471 of the C11/C++11 standards:
466 472
467 - ``add`` 473 - ``add``
468 - ``sub`` 474 - ``sub``
469 - ``or`` 475 - ``or``
470 - ``and`` 476 - ``and``
471 - ``xor`` 477 - ``xor``
472 - ``exchange`` 478 - ``exchange``
473 479
474 For all of these read-modify-write operations, the returned value is 480 For all of these read-modify-write operations, the returned value is
475 that at ``object`` before the computation. The ``computation`` 481 that at ``object`` before the computation. The ``computation`` argument
476 argument must be a compile-time constant. 482 must be a compile-time constant.
477 483
478 All atomic intrinsics also support C11/C++11 memory orderings, which 484 All atomic intrinsics also support C11/C++11 memory orderings, which
479 must be compile-time constants. Those are detailed in `Atomic Memory 485 must be compile-time constants. Those are detailed in `Atomic Memory
480 Ordering Constraints`_. 486 Ordering Constraints`_.
481 487
482 Integer values for these computations and memory orderings are defined 488 Integer values for these computations and memory orderings are defined
483 in ``"llvm/IR/NaClAtomicIntrinsics.h"``. 489 in ``"llvm/IR/NaClAtomicIntrinsics.h"``.
484 490
485 .. note:: 491 .. note::
486 492
487 These intrinsics allow PNaCl to support C11/C++11 style atomic 493 These intrinsics allow PNaCl to support C11/C++11 style atomic
488 operations as well as some legacy GCC-style ``__sync_*`` builtins 494 operations as well as some legacy GCC-style ``__sync_*`` builtins
489 while remaining stable as the LLVM codebase changes. The user 495 while remaining stable as the LLVM codebase changes. The user isn't
490 isn't expected to use these intrinsics directly. 496 expected to use these intrinsics directly.
491 497
492 .. code-block:: llvm 498 .. code-block:: llvm
493 499
494 declare i1 @llvm.nacl.atomic.is.lock.free(i32 <byte_size>, i8* <address>) 500 declare i1 @llvm.nacl.atomic.is.lock.free(i32 <byte_size>, i8* <address>)
495 501
496 The ``llvm.nacl.atomic.is.lock.free`` intrinsic is designed to 502 The ``llvm.nacl.atomic.is.lock.free`` intrinsic is designed to
497 determine at translation time whether atomic operations of a certain 503 determine at translation time whether atomic operations of a certain
498 ``byte_size`` (a compile-time constant), at a particular ``address``, 504 ``byte_size`` (a compile-time constant), at a particular ``address``,
499 are lock-free or not. This reflects the C11 ``atomic_is_lock_free`` 505 are lock-free or not. This reflects the C11 ``atomic_is_lock_free``
500 function from header ``<stdatomic.h>`` and the C++11 ``is_lock_free`` 506 function from header ``<stdatomic.h>`` and the C++11 ``is_lock_free``
501 member function in header ``<atomic>``. It can be used through the 507 member function in header ``<atomic>``. It can be used through the
502 ``__nacl_atomic_is_lock_free`` builtin. 508 ``__nacl_atomic_is_lock_free`` builtin.
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