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Side by Side Diff: test/unittests/compiler/arm64/instruction-selector-arm64-unittest.cc

Issue 2220973002: [turbofan] Remove the FloatXXSubPreserveNan operators. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Reintroduce an optimization for arm. Created 4 years, 4 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "test/unittests/compiler/instruction-selector-unittest.h" 5 #include "test/unittests/compiler/instruction-selector-unittest.h"
6 6
7 namespace v8 { 7 namespace v8 {
8 namespace internal { 8 namespace internal {
9 namespace compiler { 9 namespace compiler {
10 10
(...skipping 4201 matching lines...) Expand 10 before | Expand all | Expand 10 after
4212 Stream s = m.Build(); 4212 Stream s = m.Build();
4213 ASSERT_EQ(1U, s.size()); 4213 ASSERT_EQ(1U, s.size());
4214 EXPECT_EQ(kArm64Float64Abs, s[0]->arch_opcode()); 4214 EXPECT_EQ(kArm64Float64Abs, s[0]->arch_opcode());
4215 ASSERT_EQ(1U, s[0]->InputCount()); 4215 ASSERT_EQ(1U, s[0]->InputCount());
4216 EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); 4216 EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
4217 ASSERT_EQ(1U, s[0]->OutputCount()); 4217 ASSERT_EQ(1U, s[0]->OutputCount());
4218 EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); 4218 EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
4219 } 4219 }
4220 4220
4221 4221
4222 TEST_F(InstructionSelectorTest, Float64SubWithMinusZero) {
4223 StreamBuilder m(this, MachineType::Float64(), MachineType::Float64());
4224 Node* const p0 = m.Parameter(0);
4225 Node* const n = m.Float64Sub(m.Float64Constant(-0.0), p0);
4226 m.Return(n);
4227 Stream s = m.Build();
4228 ASSERT_EQ(1U, s.size());
4229 EXPECT_EQ(kArm64Float64Neg, s[0]->arch_opcode());
4230 ASSERT_EQ(1U, s[0]->InputCount());
4231 EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
4232 ASSERT_EQ(1U, s[0]->OutputCount());
4233 EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
4234 }
4235
4236
4237 TEST_F(InstructionSelectorTest, Float64Max) { 4222 TEST_F(InstructionSelectorTest, Float64Max) {
4238 StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(), 4223 StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(),
4239 MachineType::Float64()); 4224 MachineType::Float64());
4240 Node* const p0 = m.Parameter(0); 4225 Node* const p0 = m.Parameter(0);
4241 Node* const p1 = m.Parameter(1); 4226 Node* const p1 = m.Parameter(1);
4242 Node* const n = m.Float64Max(p0, p1); 4227 Node* const n = m.Float64Max(p0, p1);
4243 m.Return(n); 4228 m.Return(n);
4244 Stream s = m.Build(); 4229 Stream s = m.Build();
4245 ASSERT_EQ(1U, s.size()); 4230 ASSERT_EQ(1U, s.size());
4246 EXPECT_EQ(kArm64Float64Max, s[0]->arch_opcode()); 4231 EXPECT_EQ(kArm64Float64Max, s[0]->arch_opcode());
(...skipping 48 matching lines...) Expand 10 before | Expand all | Expand 10 after
4295 EXPECT_EQ(kArm64Float64Neg, s[0]->arch_opcode()); 4280 EXPECT_EQ(kArm64Float64Neg, s[0]->arch_opcode());
4296 ASSERT_EQ(1U, s[0]->InputCount()); 4281 ASSERT_EQ(1U, s[0]->InputCount());
4297 EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); 4282 EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
4298 ASSERT_EQ(1U, s[0]->OutputCount()); 4283 ASSERT_EQ(1U, s[0]->OutputCount());
4299 EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); 4284 EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
4300 } 4285 }
4301 4286
4302 } // namespace compiler 4287 } // namespace compiler
4303 } // namespace internal 4288 } // namespace internal
4304 } // namespace v8 4289 } // namespace v8
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