[turbofan] Remove the FloatXXSubPreserveNan operators.

src/mips/macro-assembler-mips.h

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
 #define V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
 
 #include "src/assembler.h"
 #include "src/globals.h"
 #include "src/mips/assembler-mips.h"
@@ skipping 857 matching lines @@
 
   // Convert double to unsigned word.
   void Trunc_uw_d(FPURegister fd, FPURegister fs, FPURegister scratch);
   void Trunc_uw_d(FPURegister fd, Register rs, FPURegister scratch);
 
   void Trunc_w_d(FPURegister fd, FPURegister fs);
   void Round_w_d(FPURegister fd, FPURegister fs);
   void Floor_w_d(FPURegister fd, FPURegister fs);
   void Ceil_w_d(FPURegister fd, FPURegister fs);
 
-  // Preserve value of a NaN operand
-  void SubNanPreservePayloadAndSign_s(FPURegister fd, FPURegister fs,
-                                      FPURegister ft);
-  void SubNanPreservePayloadAndSign_d(FPURegister fd, FPURegister fs,
-                                      FPURegister ft);
-
   // FP32 mode: Move the general purpose register into
   // the high part of the double-register pair.
   // FP64 mode: Move the general-purpose register into
   // the higher 32 bits of the 64-bit coprocessor register,
   // while leaving the low bits unchanged.
   void Mthc1(Register rt, FPURegister fs);
 
   // FP32 mode: move the high part of the double-register pair into
   // general purpose register.
   // FP64 mode: Move the higher 32 bits of the 64-bit coprocessor register into
@@ skipping 1021 matching lines @@
     dd(GetLabelFunction(index));
   }
 }
 
 #define ACCESS_MASM(masm) masm->
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_MIPS_MACRO_ASSEMBLER_MIPS_H_