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Side by Side Diff: src/compiler/mips64/instruction-selector-mips64.cc

Issue 2220973002: [turbofan] Remove the FloatXXSubPreserveNan operators. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Reintroduce an optimization for arm. Created 4 years, 4 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/base/adapters.h" 5 #include "src/base/adapters.h"
6 #include "src/base/bits.h" 6 #include "src/base/bits.h"
7 #include "src/compiler/instruction-selector-impl.h" 7 #include "src/compiler/instruction-selector-impl.h"
8 #include "src/compiler/node-matchers.h" 8 #include "src/compiler/node-matchers.h"
9 #include "src/compiler/node-properties.h" 9 #include "src/compiler/node-properties.h"
10 10
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1162 1162
1163 void InstructionSelector::VisitFloat64Add(Node* node) { 1163 void InstructionSelector::VisitFloat64Add(Node* node) {
1164 VisitRRR(this, kMips64AddD, node); 1164 VisitRRR(this, kMips64AddD, node);
1165 } 1165 }
1166 1166
1167 1167
1168 void InstructionSelector::VisitFloat32Sub(Node* node) { 1168 void InstructionSelector::VisitFloat32Sub(Node* node) {
1169 VisitRRR(this, kMips64SubS, node); 1169 VisitRRR(this, kMips64SubS, node);
1170 } 1170 }
1171 1171
1172 void InstructionSelector::VisitFloat32SubPreserveNan(Node* node) {
1173 VisitRRR(this, kMips64SubPreserveNanS, node);
1174 }
1175
1176 void InstructionSelector::VisitFloat64Sub(Node* node) { 1172 void InstructionSelector::VisitFloat64Sub(Node* node) {
1177 Mips64OperandGenerator g(this);
1178 Float64BinopMatcher m(node);
1179 if (m.left().IsMinusZero() && m.right().IsFloat64RoundDown() &&
1180 CanCover(m.node(), m.right().node())) {
1181 if (m.right().InputAt(0)->opcode() == IrOpcode::kFloat64Sub &&
1182 CanCover(m.right().node(), m.right().InputAt(0))) {
1183 Float64BinopMatcher mright0(m.right().InputAt(0));
1184 if (mright0.left().IsMinusZero()) {
1185 Emit(kMips64Float64RoundUp, g.DefineAsRegister(node),
1186 g.UseRegister(mright0.right().node()));
1187 return;
1188 }
1189 }
1190 }
1191 VisitRRR(this, kMips64SubD, node); 1173 VisitRRR(this, kMips64SubD, node);
1192 } 1174 }
1193 1175
1194 void InstructionSelector::VisitFloat64SubPreserveNan(Node* node) {
1195 VisitRRR(this, kMips64SubPreserveNanD, node);
1196 }
1197
1198 void InstructionSelector::VisitFloat32Mul(Node* node) { 1176 void InstructionSelector::VisitFloat32Mul(Node* node) {
1199 VisitRRR(this, kMips64MulS, node); 1177 VisitRRR(this, kMips64MulS, node);
1200 } 1178 }
1201 1179
1202 1180
1203 void InstructionSelector::VisitFloat64Mul(Node* node) { 1181 void InstructionSelector::VisitFloat64Mul(Node* node) {
1204 VisitRRR(this, kMips64MulD, node); 1182 VisitRRR(this, kMips64MulD, node);
1205 } 1183 }
1206 1184
1207 1185
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2159 } else { 2137 } else {
2160 DCHECK(kArchVariant == kMips64r2); 2138 DCHECK(kArchVariant == kMips64r2);
2161 return MachineOperatorBuilder::AlignmentRequirements:: 2139 return MachineOperatorBuilder::AlignmentRequirements::
2162 NoUnalignedAccessSupport(); 2140 NoUnalignedAccessSupport();
2163 } 2141 }
2164 } 2142 }
2165 2143
2166 } // namespace compiler 2144 } // namespace compiler
2167 } // namespace internal 2145 } // namespace internal
2168 } // namespace v8 2146 } // namespace v8
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