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| 1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
| 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
| 7 | 7 |
| 8 namespace v8 { | 8 namespace v8 { |
| 9 namespace internal { | 9 namespace internal { |
| 10 namespace compiler { | 10 namespace compiler { |
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| 59 V(Mips64Dshr) \ | 59 V(Mips64Dshr) \ |
| 60 V(Mips64Dsar) \ | 60 V(Mips64Dsar) \ |
| 61 V(Mips64Ror) \ | 61 V(Mips64Ror) \ |
| 62 V(Mips64Dror) \ | 62 V(Mips64Dror) \ |
| 63 V(Mips64Mov) \ | 63 V(Mips64Mov) \ |
| 64 V(Mips64Tst) \ | 64 V(Mips64Tst) \ |
| 65 V(Mips64Cmp) \ | 65 V(Mips64Cmp) \ |
| 66 V(Mips64CmpS) \ | 66 V(Mips64CmpS) \ |
| 67 V(Mips64AddS) \ | 67 V(Mips64AddS) \ |
| 68 V(Mips64SubS) \ | 68 V(Mips64SubS) \ |
| 69 V(Mips64SubPreserveNanS) \ | |
| 70 V(Mips64MulS) \ | 69 V(Mips64MulS) \ |
| 71 V(Mips64DivS) \ | 70 V(Mips64DivS) \ |
| 72 V(Mips64ModS) \ | 71 V(Mips64ModS) \ |
| 73 V(Mips64AbsS) \ | 72 V(Mips64AbsS) \ |
| 74 V(Mips64NegS) \ | 73 V(Mips64NegS) \ |
| 75 V(Mips64SqrtS) \ | 74 V(Mips64SqrtS) \ |
| 76 V(Mips64MaxS) \ | 75 V(Mips64MaxS) \ |
| 77 V(Mips64MinS) \ | 76 V(Mips64MinS) \ |
| 78 V(Mips64CmpD) \ | 77 V(Mips64CmpD) \ |
| 79 V(Mips64AddD) \ | 78 V(Mips64AddD) \ |
| 80 V(Mips64SubD) \ | 79 V(Mips64SubD) \ |
| 81 V(Mips64SubPreserveNanD) \ | |
| 82 V(Mips64MulD) \ | 80 V(Mips64MulD) \ |
| 83 V(Mips64DivD) \ | 81 V(Mips64DivD) \ |
| 84 V(Mips64ModD) \ | 82 V(Mips64ModD) \ |
| 85 V(Mips64AbsD) \ | 83 V(Mips64AbsD) \ |
| 86 V(Mips64NegD) \ | 84 V(Mips64NegD) \ |
| 87 V(Mips64SqrtD) \ | 85 V(Mips64SqrtD) \ |
| 88 V(Mips64MaxD) \ | 86 V(Mips64MaxD) \ |
| 89 V(Mips64MinD) \ | 87 V(Mips64MinD) \ |
| 90 V(Mips64Float64RoundDown) \ | 88 V(Mips64Float64RoundDown) \ |
| 91 V(Mips64Float64RoundTruncate) \ | 89 V(Mips64Float64RoundTruncate) \ |
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| 176 #define TARGET_ADDRESSING_MODE_LIST(V) \ | 174 #define TARGET_ADDRESSING_MODE_LIST(V) \ |
| 177 V(MRI) /* [%r0 + K] */ \ | 175 V(MRI) /* [%r0 + K] */ \ |
| 178 V(MRR) /* [%r0 + %r1] */ | 176 V(MRR) /* [%r0 + %r1] */ |
| 179 | 177 |
| 180 | 178 |
| 181 } // namespace compiler | 179 } // namespace compiler |
| 182 } // namespace internal | 180 } // namespace internal |
| 183 } // namespace v8 | 181 } // namespace v8 |
| 184 | 182 |
| 185 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 183 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
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