Land BoringSSL roll on master

third_party/boringssl/linux-arm/crypto/sha/sha512-armv4.S

 #if defined(__arm__)
 
 @ ====================================================================
 @ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
 @ project. The module is, however, dual licensed under OpenSSL and
 @ CRYPTOGAMS licenses depending on where you obtain it. For further
 @ details see http://www.openssl.org/~appro/cryptogams/.
 @
 @ Permission to use under GPL terms is granted.
 @ ====================================================================
@@ skipping 29 matching lines @@
 @ for further details. On side note Cortex-A15 processes one byte in
 @ 16 cycles.
 
 @ Byte order [in]dependence. =========================================
 @
 @ Originally caller was expected to maintain specific *dword* order in
 @ h[0-7], namely with most significant dword at *lower* address, which
 @ was reflected in below two parameters as 0 and 4. Now caller is
 @ expected to maintain native byte order for whole 64-bit values.
 #ifndef __KERNEL__
-# include "arm_arch.h"
+# include <openssl/arm_arch.h>
 # define VFP_ABI_PUSH   vstmdb  sp!,{d8-d15}
 # define VFP_ABI_POP    vldmia  sp!,{d8-d15}
 #else
 # define __ARM_ARCH__ __LINUX_ARM_ARCH__
 # define __ARM_MAX_ARCH__ 7
 # define VFP_ABI_PUSH
 # define VFP_ABI_POP
 #endif
 
 #ifdef __ARMEL__
@@ skipping 65 matching lines @@
 .size   K512,.-K512
 #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
 .LOPENSSL_armcap:
 .word   OPENSSL_armcap_P-.Lsha512_block_data_order
 .skip   32-4
 #else
 .skip   32
 #endif
 
 .globl  sha512_block_data_order
+.hidden sha512_block_data_order
 .type   sha512_block_data_order,%function
 sha512_block_data_order:
 .Lsha512_block_data_order:
 #if __ARM_ARCH__<7
         sub     r3,pc,#8                @ sha512_block_data_order
 #else
         adr     r3,sha512_block_data_order
 #endif
 #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
         ldr     r12,.LOPENSSL_armcap
         ldr     r12,[r3,r12]            @ OPENSSL_armcap_P
 #ifdef  __APPLE__
         ldr     r12,[r12]
 #endif
-        tst     r12,#1
+        tst     r12,#ARMV7_NEON
         bne     .LNEON
 #endif
         add     r2,r1,r2,lsl#7  @ len to point at the end of inp
         stmdb   sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
         sub     r14,r3,#672             @ K512
         sub     sp,sp,#9*8
 
         ldr     r7,[r0,#32+LO]
         ldr     r8,[r0,#32+HI]
         ldr     r9, [r0,#48+LO]
@@ skipping 365 matching lines @@
         tst     lr,#1
         moveq   pc,lr                   @ be binary compatible with V4, yet
 .word   0xe12fff1e                      @ interoperable with Thumb ISA:-)
 #endif
 .size   sha512_block_data_order,.-sha512_block_data_order
 #if __ARM_MAX_ARCH__>=7
 .arch   armv7-a
 .fpu    neon
 
 .globl  sha512_block_data_order_neon
+.hidden sha512_block_data_order_neon
 .type   sha512_block_data_order_neon,%function
 .align  4
 sha512_block_data_order_neon:
 .LNEON:
         dmb     @ errata #451034 on early Cortex A8
         add     r2,r1,r2,lsl#7  @ len to point at the end of inp
         adr     r3,K512
         VFP_ABI_PUSH
         vldmia  r0,{d16,d17,d18,d19,d20,d21,d22,d23}            @ load context
 .Loop_neon:
@@ skipping 1313 matching lines @@
         bx      lr                              @ .word 0xe12fff1e
 .size   sha512_block_data_order_neon,.-sha512_block_data_order_neon
 #endif
 .byte   83,72,65,53,49,50,32,98,108,111,99,107,32,116,114,97,110,115,102,111,114,109,32,102,111,114,32,65,82,77,118,52,47,78,69,79,78,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
 .align  2
 .align  2
 #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
 .comm   OPENSSL_armcap_P,4,4
 .hidden OPENSSL_armcap_P
 #endif
-#endif
+#endif