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| 1 //===- subzero/src/IceClFlags.def - Cl Flags for translation ----*- C++ -*-===// | 1 //===- subzero/src/IceClFlags.def - Cl Flags for translation ----*- C++ -*-===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
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| 146 \ | 146 \ |
| 147 X(LocalCSE, Ice::LCSEOptions, dev_opt_flag, "lcse", \ | 147 X(LocalCSE, Ice::LCSEOptions, dev_opt_flag, "lcse", \ |
| 148 cl::desc("Local common subexpression elimination"), \ | 148 cl::desc("Local common subexpression elimination"), \ |
| 149 cl::init(Ice::LCSE_EnabledSSA), \ | 149 cl::init(Ice::LCSE_EnabledSSA), \ |
| 150 cl::values( \ | 150 cl::values( \ |
| 151 clEnumValN(Ice::LCSE_Disabled, "0", "disabled"), \ | 151 clEnumValN(Ice::LCSE_Disabled, "0", "disabled"), \ |
| 152 clEnumValN(Ice::LCSE_EnabledSSA, "enabled", "assume-ssa"), \ | 152 clEnumValN(Ice::LCSE_EnabledSSA, "enabled", "assume-ssa"), \ |
| 153 clEnumValN(Ice::LCSE_EnabledNoSSA, "no-ssa", "no-assume-ssa"), \ | 153 clEnumValN(Ice::LCSE_EnabledNoSSA, "no-ssa", "no-assume-ssa"), \ |
| 154 clEnumValEnd)) \ | 154 clEnumValEnd)) \ |
| 155 \ | 155 \ |
| 156 X(EmitRevision, bool, dev_opt_flag, "emit-revision", \ |
| 157 cl::desc("Emit Subzero revision string into the output"), cl::init(true)) \ |
| 158 \ |
| 156 X(EnablePhiEdgeSplit, bool, dev_opt_flag, "phi-edge-split", \ | 159 X(EnablePhiEdgeSplit, bool, dev_opt_flag, "phi-edge-split", \ |
| 157 cl::desc("Enable edge splitting for Phi lowering"), cl::init(true)) \ | 160 cl::desc("Enable edge splitting for Phi lowering"), cl::init(true)) \ |
| 158 \ | 161 \ |
| 159 X(EnableShortCircuit, bool, dev_opt_flag, "enable-sc", \ | 162 X(EnableShortCircuit, bool, dev_opt_flag, "enable-sc", \ |
| 160 cl::desc("Split Nodes for short circuit evaluation"), cl::init(false)) \ | 163 cl::desc("Split Nodes for short circuit evaluation"), cl::init(false)) \ |
| 161 \ | 164 \ |
| 162 X(ExcludedRegisters, std::string, dev_list_flag, "reg-exclude", \ | 165 X(ExcludedRegisters, std::string, dev_list_flag, "reg-exclude", \ |
| 163 cl::CommaSeparated, cl::desc("Don't use specified registers")) \ | 166 cl::CommaSeparated, cl::desc("Don't use specified registers")) \ |
| 164 \ | 167 \ |
| 165 X(ForceMemIntrinOpt, bool, dev_opt_flag, "fmem-intrin-opt", \ | 168 X(ForceMemIntrinOpt, bool, dev_opt_flag, "fmem-intrin-opt", \ |
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| 386 \ | 389 \ |
| 387 X(WasmBoundsCheck, bool, dev_opt_flag, "wasm-bounds-check", \ | 390 X(WasmBoundsCheck, bool, dev_opt_flag, "wasm-bounds-check", \ |
| 388 cl::desc("Add bounds checking code in WASM frontend"), \ | 391 cl::desc("Add bounds checking code in WASM frontend"), \ |
| 389 cl::init(true)) | 392 cl::init(true)) |
| 390 | 393 |
| 391 //#define X(Name, Type, ClType, ...) | 394 //#define X(Name, Type, ClType, ...) |
| 392 | 395 |
| 393 } // end of namespace Ice | 396 } // end of namespace Ice |
| 394 | 397 |
| 395 #endif // SUBZERO_SRC_ICECLFLAGS_DEF | 398 #endif // SUBZERO_SRC_ICECLFLAGS_DEF |
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