Subzero: Use Cfg::getOptLevel() instead of ClFlags version.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 2204 matching lines @@
   // bit-manipulation problems below.
   const uint32_t AlignmentParam = std::max(1u, Instr->getAlignInBytes());
 
   // LLVM enforces power of 2 alignment.
   assert(llvm::isPowerOf2_32(AlignmentParam));
   assert(llvm::isPowerOf2_32(ARM32_STACK_ALIGNMENT_BYTES));
 
   const uint32_t Alignment =
       std::max(AlignmentParam, ARM32_STACK_ALIGNMENT_BYTES);
   const bool OverAligned = Alignment > ARM32_STACK_ALIGNMENT_BYTES;
-  const bool OptM1 = getFlags().getOptLevel() == Opt_m1;
+  const bool OptM1 = Func->getOptLevel() == Opt_m1;
   const bool AllocaWithKnownOffset = Instr->getKnownFrameOffset();
   const bool UseFramePointer =
       hasFramePointer() || OverAligned || !AllocaWithKnownOffset || OptM1;
 
   if (UseFramePointer)
     setHasFramePointer();
 
   Variable *SP = getPhysicalRegister(RegARM32::Reg_sp);
   if (OverAligned) {
     Sandboxer(this).align_sp(Alignment);
@@ skipping 1083 matching lines @@
     Variable *Src1R = Srcs.unswappedSrc1R(this);
     if (isVectorType(DestTy)) {
       _vsub(T, Src0R, Src1R);
     } else {
       _sub(T, Src0R, Src1R);
     }
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Mul: {
-    const bool OptM1 = getFlags().getOptLevel() == Opt_m1;
+    const bool OptM1 = Func->getOptLevel() == Opt_m1;
     if (!OptM1 && Srcs.hasConstOperand()) {
       constexpr std::size_t MaxShifts = 4;
       std::array<StrengthReduction::AggregationElement, MaxShifts> Shifts;
       SizeT NumOperations;
       int32_t Const = Srcs.getConstantValue();
       const bool Invert = Const < 0;
       const bool MultiplyByZero = Const == 0;
       Operand *_0 =
           legalize(Ctx->getConstantZero(DestTy), Legal_Reg | Legal_Flex);
 
@@ skipping 3025 matching lines @@
                     TmpRegNum);
     _bic(Reg, Reg, Mask);
   } else {
     Mask = legalize(Ctx->getConstantInt32(-Align), Legal_Reg | Legal_Flex,
                     TmpRegNum);
     _and(Reg, Reg, Mask);
   }
 }
 
 void TargetARM32::postLower() {
-  if (getFlags().getOptLevel() == Opt_m1)
+  if (Func->getOptLevel() == Opt_m1)
     return;
   markRedefinitions();
   Context.availabilityUpdate();
 }
 
 void TargetARM32::makeRandomRegisterPermutation(
     llvm::SmallVectorImpl<RegNumT> &Permutation,
     const SmallBitVector &ExcludeRegisters, uint64_t Salt) const {
   (void)Permutation;
   (void)ExcludeRegisters;
@@ skipping 761 matching lines @@
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 
 } // end of namespace ARM32
 } // end of namespace Ice