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Unified Diff: src/atomicops_internals_arm64_gcc.h

Issue 220793002: ARM64: Fix and improve atomic operations. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 9 months ago
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Index: src/atomicops_internals_arm64_gcc.h
diff --git a/src/atomicops_internals_arm64_gcc.h b/src/atomicops_internals_arm64_gcc.h
index e6cac19932ad6858311178b8f83f1ffd4f6bd6be..c75b081456ce7f674da319ac5299f73152862e59 100644
--- a/src/atomicops_internals_arm64_gcc.h
+++ b/src/atomicops_internals_arm64_gcc.h
@@ -34,13 +34,9 @@ namespace v8 {
namespace internal {
inline void MemoryBarrier() {
- __asm__ __volatile__ ( // NOLINT
- "dmb ish \n\t" // Data memory barrier.
- ::: "memory"
- ); // NOLINT
+ __asm__ __volatile__ ("dmb ish" ::: "memory"); // NOLINT
}
-
inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
Atomic32 old_value,
Atomic32 new_value) {
@@ -55,13 +51,12 @@ inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
"stxr %w[temp], %w[new_value], %[ptr] \n\t" // Try to store the new value.
"cbnz %w[temp], 0b \n\t" // Retry if it did not work.
"1: \n\t"
- "clrex \n\t" // In case we didn't swap.
: [prev]"=&r" (prev),
[temp]"=&r" (temp),
[ptr]"+Q" (*ptr)
- : [old_value]"r" (old_value),
+ : [old_value]"IJr" (old_value),
rmcilroy 2014/04/01 10:41:19 Do the I and J constraints require that the value
Alexandre Rames 2014/04/01 10:50:55 It is just a hint. If the value does not fit it wi
[new_value]"r" (new_value)
- : "memory", "cc"
+ : "cc"
); // NOLINT
return prev;
@@ -81,7 +76,7 @@ inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
[temp]"=&r" (temp),
[ptr]"+Q" (*ptr)
: [new_value]"r" (new_value)
- : "memory"
+ :
); // NOLINT
return result;
@@ -101,8 +96,8 @@ inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
: [result]"=&r" (result),
[temp]"=&r" (temp),
[ptr]"+Q" (*ptr)
- : [increment]"r" (increment)
- : "memory"
+ : [increment]"IJr" (increment)
+ :
); // NOLINT
return result;
@@ -110,8 +105,10 @@ inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
Atomic32 increment) {
+ Atomic32 result;
+
MemoryBarrier();
- Atomic32 result = NoBarrier_AtomicIncrement(ptr, increment);
+ result = NoBarrier_AtomicIncrement(ptr, increment);
MemoryBarrier();
return result;
@@ -121,27 +118,9 @@ inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
Atomic32 old_value,
Atomic32 new_value) {
Atomic32 prev;
- int32_t temp;
- __asm__ __volatile__ ( // NOLINT
- "0: \n\t"
- "ldxr %w[prev], %[ptr] \n\t" // Load the previous value.
- "cmp %w[prev], %w[old_value] \n\t"
- "bne 1f \n\t"
- "stxr %w[temp], %w[new_value], %[ptr] \n\t" // Try to store the new value.
- "cbnz %w[temp], 0b \n\t" // Retry if it did not work.
- "dmb ish \n\t" // Data memory barrier.
- "1: \n\t"
- // If the compare failed the 'dmb' is unnecessary, but we still need a
- // 'clrex'.
- "clrex \n\t"
- : [prev]"=&r" (prev),
- [temp]"=&r" (temp),
- [ptr]"+Q" (*ptr)
- : [old_value]"r" (old_value),
- [new_value]"r" (new_value)
- : "memory", "cc"
- ); // NOLINT
+ prev = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
+ MemoryBarrier();
return prev;
}
@@ -150,27 +129,9 @@ inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
Atomic32 old_value,
Atomic32 new_value) {
Atomic32 prev;
- int32_t temp;
MemoryBarrier();
-
- __asm__ __volatile__ ( // NOLINT
- "0: \n\t"
- "ldxr %w[prev], %[ptr] \n\t" // Load the previous value.
- "cmp %w[prev], %w[old_value] \n\t"
- "bne 1f \n\t"
- "stxr %w[temp], %w[new_value], %[ptr] \n\t" // Try to store the new value.
- "cbnz %w[temp], 0b \n\t" // Retry if it did not work.
- "1: \n\t"
- // If the compare failed the we still need a 'clrex'.
- "clrex \n\t"
- : [prev]"=&r" (prev),
- [temp]"=&r" (temp),
- [ptr]"+Q" (*ptr)
- : [old_value]"r" (old_value),
- [new_value]"r" (new_value)
- : "memory", "cc"
- ); // NOLINT
+ prev = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
return prev;
}
@@ -185,8 +146,12 @@ inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
}
inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
- MemoryBarrier();
- *ptr = value;
+ __asm__ __volatile__ ( // NOLINT
+ "stlr %w[value], %[ptr] \n\t"
+ : [ptr]"=Q" (*ptr)
+ : [value]"r" (value)
+ : "memory"
+ ); // NOLINT
}
inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) {
@@ -194,8 +159,15 @@ inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) {
}
inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) {
- Atomic32 value = *ptr;
- MemoryBarrier();
+ Atomic32 value;
+
+ __asm__ __volatile__ ( // NOLINT
+ "ldar %w[value], %[ptr] \n\t"
+ : [value]"=r" (value)
+ : [ptr]"Q" (*ptr)
+ : "memory"
+ ); // NOLINT
+
return value;
}
@@ -221,13 +193,12 @@ inline Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr,
"stxr %w[temp], %[new_value], %[ptr] \n\t"
"cbnz %w[temp], 0b \n\t"
"1: \n\t"
- "clrex \n\t"
: [prev]"=&r" (prev),
[temp]"=&r" (temp),
[ptr]"+Q" (*ptr)
- : [old_value]"r" (old_value),
+ : [old_value]"IJr" (old_value),
[new_value]"r" (new_value)
- : "memory", "cc"
+ : "cc"
); // NOLINT
return prev;
@@ -247,7 +218,7 @@ inline Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr,
[temp]"=&r" (temp),
[ptr]"+Q" (*ptr)
: [new_value]"r" (new_value)
- : "memory"
+ :
); // NOLINT
return result;
@@ -267,8 +238,8 @@ inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr,
: [result]"=&r" (result),
[temp]"=&r" (temp),
[ptr]"+Q" (*ptr)
- : [increment]"r" (increment)
- : "memory"
+ : [increment]"IJr" (increment)
+ :
); // NOLINT
return result;
@@ -276,8 +247,10 @@ inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr,
inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr,
Atomic64 increment) {
+ Atomic64 result;
+
MemoryBarrier();
- Atomic64 result = NoBarrier_AtomicIncrement(ptr, increment);
+ result = NoBarrier_AtomicIncrement(ptr, increment);
MemoryBarrier();
return result;
@@ -287,25 +260,9 @@ inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
Atomic64 old_value,
Atomic64 new_value) {
Atomic64 prev;
- int32_t temp;
- __asm__ __volatile__ ( // NOLINT
- "0: \n\t"
- "ldxr %[prev], %[ptr] \n\t"
- "cmp %[prev], %[old_value] \n\t"
- "bne 1f \n\t"
- "stxr %w[temp], %[new_value], %[ptr] \n\t"
- "cbnz %w[temp], 0b \n\t"
- "dmb ish \n\t"
- "1: \n\t"
- "clrex \n\t"
- : [prev]"=&r" (prev),
- [temp]"=&r" (temp),
- [ptr]"+Q" (*ptr)
- : [old_value]"r" (old_value),
- [new_value]"r" (new_value)
- : "memory", "cc"
- ); // NOLINT
+ prev = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
+ MemoryBarrier();
return prev;
}
@@ -314,26 +271,9 @@ inline Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr,
Atomic64 old_value,
Atomic64 new_value) {
Atomic64 prev;
- int32_t temp;
MemoryBarrier();
-
- __asm__ __volatile__ ( // NOLINT
- "0: \n\t"
- "ldxr %[prev], %[ptr] \n\t"
- "cmp %[prev], %[old_value] \n\t"
- "bne 1f \n\t"
- "stxr %w[temp], %[new_value], %[ptr] \n\t"
- "cbnz %w[temp], 0b \n\t"
- "1: \n\t"
- "clrex \n\t"
- : [prev]"=&r" (prev),
- [temp]"=&r" (temp),
- [ptr]"+Q" (*ptr)
- : [old_value]"r" (old_value),
- [new_value]"r" (new_value)
- : "memory", "cc"
- ); // NOLINT
+ prev = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
return prev;
}
@@ -348,8 +288,12 @@ inline void Acquire_Store(volatile Atomic64* ptr, Atomic64 value) {
}
inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) {
- MemoryBarrier();
- *ptr = value;
+ __asm__ __volatile__ ( // NOLINT
+ "stlr %x[value], %[ptr] \n\t"
+ : [ptr]"=Q" (*ptr)
+ : [value]"r" (value)
+ : "memory"
+ ); // NOLINT
}
inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptr) {
@@ -357,8 +301,15 @@ inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptr) {
}
inline Atomic64 Acquire_Load(volatile const Atomic64* ptr) {
- Atomic64 value = *ptr;
- MemoryBarrier();
+ Atomic32 value;
+
+ __asm__ __volatile__ ( // NOLINT
+ "ldar %x[value], %[ptr] \n\t"
+ : [value]"=r" (value)
+ : [ptr]"Q" (*ptr)
+ : "memory"
+ ); // NOLINT
+
return value;
}
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