SubZero: Adding support for all Reg pairs in getI64PairFirst/SecondGPRNum

src/IceRegistersMIPS32.h

 //===- subzero/src/IceRegistersMIPS32.h - Register information --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 71 matching lines @@
   return FPRRegister(RegNum - Reg_FPR_First);
 }
 
 static inline bool isFPRReg(RegNumT RegNum) {
   return (int(Reg_FPR_First) <= int(RegNum)) &&
          (unsigned(RegNum) <= Reg_FPR_Last);
 }
 
 const char *getRegName(RegNumT RegNum);
 
-static inline RegNumT getI64PairFirstGPRNum(RegNumT RegNum) {
-  // For now it works only for argument register pairs
-  // TODO(mohit.bhakkad): Change this to support all the register pairs once we
-  // have table-driven approach ready
-  assert(RegNum == Reg_A0A1 || RegNum == Reg_A2A3);
-  return (RegNum == RegMIPS32::Reg_A0A1) ? RegMIPS32::Reg_A0
-                                         : RegMIPS32::Reg_A2;
+static inline RegNumT get64PairFirstRegNum(RegNumT RegNum) {
+  assert(unsigned(RegNum) >= Reg_I64PAIR_First);
+  assert(unsigned(RegNum) <= Reg_F64PAIR_Last);
+  if (unsigned(RegNum) >= Reg_F64PAIR_First &&
+      unsigned(RegNum) <= Reg_F64PAIR_Last)
+    return RegNumT::fixme(((RegNum - Reg_F64PAIR_First) * 2) +
+                          unsigned(Reg_FPR_First));
+  if (unsigned(RegNum) >= Reg_I64PAIR_First &&
+           unsigned(RegNum) <= Reg_T8T9)
+    return RegNumT::fixme(((RegNum - Reg_I64PAIR_First) * 2) +
+                          unsigned(Reg_V0));
+  return RegMIPS32::Reg_LO;
 }
 
-static inline RegNumT getI64PairSecondGPRNum(RegNumT RegNum) {
-  // For now it works only for argument register pairs
-  // TODO(mohit.bhakkad): Change this to support all the register pairs once we
-  // have table-driven approach ready
-  assert(RegNum == Reg_A0A1 || RegNum == Reg_A2A3);
-  return (RegNum == RegMIPS32::Reg_A0A1) ? RegMIPS32::Reg_A1
-                                         : RegMIPS32::Reg_A3;
+static inline RegNumT get64PairSecondRegNum(RegNumT RegNum) {
+  assert(unsigned(RegNum) >= Reg_I64PAIR_First);
+  assert(unsigned(RegNum) <= Reg_F64PAIR_Last);
+  if (unsigned(RegNum) >= Reg_F64PAIR_First &&
+      unsigned(RegNum) <= Reg_F64PAIR_Last)
+    return RegNumT::fixme(((RegNum - Reg_F64PAIR_First) * 2) +
+                          unsigned(Reg_FPR_First) + 1);
+  if (unsigned(RegNum) >= Reg_I64PAIR_First &&
+           unsigned(RegNum) <= Reg_T8T9)
+    return RegNumT::fixme(((RegNum - Reg_I64PAIR_First) * 2) +
+                          unsigned(Reg_V1));
+  return RegMIPS32::Reg_HI;
 }
 
 } // end of namespace RegMIPS32
 
 // Extend enum RegClass with MIPS32-specific register classes (if any).
 enum RegClassMIPS32 : uint8_t { RCMIPS32_NUM = RC_Target };
 
 } // end of namespace MIPS32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEREGISTERSMIPS32_H