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| 1 /* Copyright (c) 2014, Cisco Systems, INC |
| 2 Written by XiangMingZhu WeiZhou MinPeng YanWang |
| 3 |
| 4 Redistribution and use in source and binary forms, with or without |
| 5 modification, are permitted provided that the following conditions |
| 6 are met: |
| 7 |
| 8 - Redistributions of source code must retain the above copyright |
| 9 notice, this list of conditions and the following disclaimer. |
| 10 |
| 11 - Redistributions in binary form must reproduce the above copyright |
| 12 notice, this list of conditions and the following disclaimer in the |
| 13 documentation and/or other materials provided with the distribution. |
| 14 |
| 15 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 16 ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 17 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 18 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER |
| 19 OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 20 EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 21 PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
| 22 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
| 23 LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
| 24 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 25 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 */ |
| 27 |
| 28 #if !defined(X86CPU_H) |
| 29 # define X86CPU_H |
| 30 |
| 31 # if defined(OPUS_X86_MAY_HAVE_SSE) |
| 32 # define MAY_HAVE_SSE(name) name ## _sse |
| 33 # else |
| 34 # define MAY_HAVE_SSE(name) name ## _c |
| 35 # endif |
| 36 |
| 37 # if defined(OPUS_X86_MAY_HAVE_SSE2) |
| 38 # define MAY_HAVE_SSE2(name) name ## _sse2 |
| 39 # else |
| 40 # define MAY_HAVE_SSE2(name) name ## _c |
| 41 # endif |
| 42 |
| 43 # if defined(OPUS_X86_MAY_HAVE_SSE4_1) |
| 44 # define MAY_HAVE_SSE4_1(name) name ## _sse4_1 |
| 45 # else |
| 46 # define MAY_HAVE_SSE4_1(name) name ## _c |
| 47 # endif |
| 48 |
| 49 # if defined(OPUS_X86_MAY_HAVE_AVX) |
| 50 # define MAY_HAVE_AVX(name) name ## _avx |
| 51 # else |
| 52 # define MAY_HAVE_AVX(name) name ## _c |
| 53 # endif |
| 54 |
| 55 # if defined(OPUS_HAVE_RTCD) |
| 56 int opus_select_arch(void); |
| 57 # endif |
| 58 |
| 59 /*gcc appears to emit MOVDQA's to load the argument of an _mm_cvtepi8_epi32() |
| 60 or _mm_cvtepi16_epi32() when optimizations are disabled, even though the |
| 61 actual PMOVSXWD instruction takes an m32 or m64. Unlike a normal memory |
| 62 reference, these require 16-byte alignment and load a full 16 bytes (instead |
| 63 of 4 or 8), possibly reading out of bounds. |
| 64 |
| 65 We can insert an explicit MOVD or MOVQ using _mm_cvtsi32_si128() or |
| 66 _mm_loadl_epi64(), which should have the same semantics as an m32 or m64 |
| 67 reference in the PMOVSXWD instruction itself, but gcc is not smart enough to |
| 68 optimize this out when optimizations ARE enabled. |
| 69 |
| 70 Clang, in contrast, requires us to do this always for _mm_cvtepi8_epi32 |
| 71 (which is fair, since technically the compiler is always allowed to do the |
| 72 dereference before invoking the function implementing the intrinsic). |
| 73 However, it is smart enough to eliminate the extra MOVD instruction. |
| 74 For _mm_cvtepi16_epi32, it does the right thing, though does *not* optimize ou
t |
| 75 the extra MOVQ if it's specified explicitly */ |
| 76 |
| 77 # if defined(__clang__) || !defined(__OPTIMIZE__) |
| 78 # define OP_CVTEPI8_EPI32_M32(x) \ |
| 79 (_mm_cvtepi8_epi32(_mm_cvtsi32_si128(*(int *)(x)))) |
| 80 # else |
| 81 # define OP_CVTEPI8_EPI32_M32(x) \ |
| 82 (_mm_cvtepi8_epi32(*(__m128i *)(x))) |
| 83 #endif |
| 84 |
| 85 # if !defined(__OPTIMIZE__) |
| 86 # define OP_CVTEPI16_EPI32_M64(x) \ |
| 87 (_mm_cvtepi16_epi32(_mm_loadl_epi64((__m128i *)(x)))) |
| 88 # else |
| 89 # define OP_CVTEPI16_EPI32_M64(x) \ |
| 90 (_mm_cvtepi16_epi32(*(__m128i *)(x))) |
| 91 # endif |
| 92 |
| 93 #endif |
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