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Side by Side Diff: src/compiler/arm64/instruction-codes-arm64.h

Issue 2183923003: [stubs,interpreter] Optimise SMI loading for 64-bit targets. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Optimizing SMI loads at code stub assembler level. Created 4 years, 4 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 5 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
6 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 6 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 129 matching lines...) Expand 10 before | Expand all | Expand 10 after
140 V(Arm64LdrS) \ 140 V(Arm64LdrS) \
141 V(Arm64StrS) \ 141 V(Arm64StrS) \
142 V(Arm64LdrD) \ 142 V(Arm64LdrD) \
143 V(Arm64StrD) \ 143 V(Arm64StrD) \
144 V(Arm64Ldrb) \ 144 V(Arm64Ldrb) \
145 V(Arm64Ldrsb) \ 145 V(Arm64Ldrsb) \
146 V(Arm64Strb) \ 146 V(Arm64Strb) \
147 V(Arm64Ldrh) \ 147 V(Arm64Ldrh) \
148 V(Arm64Ldrsh) \ 148 V(Arm64Ldrsh) \
149 V(Arm64Strh) \ 149 V(Arm64Strh) \
150 V(Arm64Ldrsw) \
150 V(Arm64LdrW) \ 151 V(Arm64LdrW) \
151 V(Arm64StrW) \ 152 V(Arm64StrW) \
152 V(Arm64Ldr) \ 153 V(Arm64Ldr) \
153 V(Arm64Str) 154 V(Arm64Str)
154 155
155 // Addressing modes represent the "shape" of inputs to an instruction. 156 // Addressing modes represent the "shape" of inputs to an instruction.
156 // Many instructions support multiple addressing modes. Addressing modes 157 // Many instructions support multiple addressing modes. Addressing modes
157 // are encoded into the InstructionCode of the instruction and tell the 158 // are encoded into the InstructionCode of the instruction and tell the
158 // code generator after register allocation which assembler method to call. 159 // code generator after register allocation which assembler method to call.
159 // 160 //
(...skipping 18 matching lines...) Expand all
178 V(Operand2_R_SXTH) /* %r0 SXTH (signed extend halfword) */ \ 179 V(Operand2_R_SXTH) /* %r0 SXTH (signed extend halfword) */ \
179 V(Operand2_R_SXTW) /* %r0 SXTW (signed extend word) */ 180 V(Operand2_R_SXTW) /* %r0 SXTW (signed extend word) */
180 181
181 enum ResetJSSPAfterCall { kNoResetJSSP, kResetJSSP }; 182 enum ResetJSSPAfterCall { kNoResetJSSP, kResetJSSP };
182 183
183 } // namespace compiler 184 } // namespace compiler
184 } // namespace internal 185 } // namespace internal
185 } // namespace v8 186 } // namespace v8
186 187
187 #endif // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 188 #endif // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
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