ARM: Implement UnaligedLoad and UnaligedStore turbofan operators.

src/compiler/arm/instruction-scheduler-arm.cc

 // Copyright 2015 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/instruction-scheduler.h"
 
 namespace v8 {
 namespace internal {
 namespace compiler {
 
@@ skipping 84 matching lines @@
     case kArmVcvtU32F32:
     case kArmVcvtS32F64:
     case kArmVcvtU32F64:
     case kArmVmovU32F32:
     case kArmVmovF32U32:
     case kArmVmovLowU32F64:
     case kArmVmovLowF64U32:
     case kArmVmovHighU32F64:
     case kArmVmovHighF64U32:
     case kArmVmovF64U32U32:
+    case kArmVmovU32U32F64:
     case kArmFloat64Max:
     case kArmFloat64Min:
     case kArmFloat64SilenceNaN:
       return kNoOpcodeFlags;
 
     case kArmVldrF32:
     case kArmVldrF64:
     case kArmLdrb:
     case kArmLdrsb:
     case kArmLdrh:
@@ skipping 23 matching lines @@
 
 
 int InstructionScheduler::GetInstructionLatency(const Instruction* instr) {
   // TODO(all): Add instruction cost modeling.
   return 1;
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8