| OLD | NEW |
| 1 ; This is a smoke test of randomized register allocation. The output | 1 ; This is a smoke test of randomized register allocation. The output |
| 2 ; of this test will change with changes to the random number generator | 2 ; of this test will change with changes to the random number generator |
| 3 ; implementation. | 3 ; implementation. |
| 4 | 4 |
| 5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -sz-seed=1 \ | 5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -sz-seed=1 \ |
| 6 ; RUN: -randomize-regalloc \ | 6 ; RUN: -randomize-regalloc -split-local-vars=0 \ |
| 7 ; RUN: | FileCheck %s --check-prefix=CHECK_1 | 7 ; RUN: | FileCheck %s --check-prefix=CHECK_1 |
| 8 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -sz-seed=1 \ | 8 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -sz-seed=1 \ |
| 9 ; RUN: -randomize-regalloc \ | 9 ; RUN: -randomize-regalloc \ |
| 10 ; RUN: | FileCheck %s --check-prefix=OPTM1_1 | 10 ; RUN: | FileCheck %s --check-prefix=OPTM1_1 |
| 11 | 11 |
| 12 ; Same tests but with a different seed, just to verify randomness. | 12 ; Same tests but with a different seed, just to verify randomness. |
| 13 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -sz-seed=123 \ | 13 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -sz-seed=123 \ |
| 14 ; RUN: -randomize-regalloc \ | 14 ; RUN: -randomize-regalloc -split-local-vars=0 \ |
| 15 ; RUN: | FileCheck %s --check-prefix=CHECK_123 | 15 ; RUN: | FileCheck %s --check-prefix=CHECK_123 |
| 16 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -sz-seed=123 \ | 16 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -sz-seed=123 \ |
| 17 ; RUN: -randomize-regalloc \ | 17 ; RUN: -randomize-regalloc \ |
| 18 ; RUN: | FileCheck %s --check-prefix=OPTM1_123 | 18 ; RUN: | FileCheck %s --check-prefix=OPTM1_123 |
| 19 | 19 |
| 20 define internal <4 x i32> @mul_v4i32(<4 x i32> %a, <4 x i32> %b) { | 20 define internal <4 x i32> @mul_v4i32(<4 x i32> %a, <4 x i32> %b) { |
| 21 entry: | 21 entry: |
| 22 %res = mul <4 x i32> %a, %b | 22 %res = mul <4 x i32> %a, %b |
| 23 ret <4 x i32> %res | 23 ret <4 x i32> %res |
| 24 ; OPTM1_1-LABEL: mul_v4i32 | 24 ; OPTM1_1-LABEL: mul_v4i32 |
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| 71 ; CHECK_123-NEXT: pmuludq xmm5,xmm1 | 71 ; CHECK_123-NEXT: pmuludq xmm5,xmm1 |
| 72 ; CHECK_123-NEXT: pmuludq xmm0,xmm7 | 72 ; CHECK_123-NEXT: pmuludq xmm0,xmm7 |
| 73 ; CHECK_123-NEXT: shufps xmm5,xmm0,0x88 | 73 ; CHECK_123-NEXT: shufps xmm5,xmm0,0x88 |
| 74 ; CHECK_123-NEXT: pshufd xmm5,xmm5,0xd8 | 74 ; CHECK_123-NEXT: pshufd xmm5,xmm5,0xd8 |
| 75 ; CHECK_123-NEXT: movups xmm0,xmm5 | 75 ; CHECK_123-NEXT: movups xmm0,xmm5 |
| 76 ; CHECK_123-NEXT: ret | 76 ; CHECK_123-NEXT: ret |
| 77 } | 77 } |
| 78 | 78 |
| 79 ; ERRORS-NOT: ICE translation error | 79 ; ERRORS-NOT: ICE translation error |
| 80 ; DUMP-NOT: SZ | 80 ; DUMP-NOT: SZ |
| OLD | NEW |