Subzero: Local variable splitting.

tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll

 ; This tests each of the supported NaCl atomic instructions for every
 ; size allowed.
 
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
 ; RUN:   -allow-externally-defined-symbols | FileCheck %s
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
 ; RUN:   -allow-externally-defined-symbols | FileCheck --check-prefix=O2 %s
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
 ; RUN:   -allow-externally-defined-symbols | FileCheck %s
 
@@ skipping 1384 matching lines @@
   %i_plus_1 = add i32 %i, 1
   %cmp = icmp eq i32 %i_plus_1, 1001
   br i1 %cmp, label %done, label %body
 done:
   ret void
 }
 ; O2-LABEL: test_xadd_regalloc
 ;;; Some register will be used in the xadd instruction.
 ; O2: lock xadd DWORD PTR {{.*}},[[REG:e..]]
 ;;; Make sure that register isn't used again, e.g. as the induction variable.
-; O2-NOT: [[REG]]
+; O2-NOT: ,[[REG]]
 ; O2: ret
 
 ; Do the same test for the xchg instruction instead of xadd.
 define internal void @test_xchg_regalloc() {
 entry:
   br label %body
 body:
   %i = phi i32 [ 1, %entry ], [ %i_plus_1, %body ]
   %g = bitcast [4 x i8]* @SzGlobal32 to i32*
   %unused = call i32 @llvm.nacl.atomic.rmw.i32(i32 6, i32* %g, i32 %i, i32 6)
   %i_plus_1 = add i32 %i, 1
   %cmp = icmp eq i32 %i_plus_1, 1001
   br i1 %cmp, label %done, label %body
 done:
   ret void
 }
 ; O2-LABEL: test_xchg_regalloc
 ;;; Some register will be used in the xchg instruction.
 ; O2: xchg DWORD PTR {{.*}},[[REG:e..]]
 ;;; Make sure that register isn't used again, e.g. as the induction variable.
-; O2-NOT: [[REG]]
+; O2-NOT: ,[[REG]]
 ; O2: ret
 
 ; Same test for cmpxchg.
 define internal void @test_cmpxchg_regalloc() {
 entry:
   br label %body
 body:
   %i = phi i32 [ 1, %entry ], [ %i_plus_1, %body ]
   %g = bitcast [4 x i8]* @SzGlobal32 to i32*
   %unused = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %g, i32 %i, i32 %i, i32 6, i32 6)
   %i_plus_1 = add i32 %i, 1
   %cmp = icmp eq i32 %i_plus_1, 1001
   br i1 %cmp, label %done, label %body
 done:
   ret void
 }
 ; O2-LABEL: test_cmpxchg_regalloc
 ;;; eax and some other register will be used in the cmpxchg instruction.
 ; O2: lock cmpxchg DWORD PTR {{.*}},[[REG:e..]]
 ;;; Make sure eax isn't used again, e.g. as the induction variable.
-; O2-NOT: eax
+; O2-NOT: ,eax
 ; O2: ret
 
 ; Same test for cmpxchg8b.
 define internal void @test_cmpxchg8b_regalloc() {
 entry:
   br label %body
 body:
   %i = phi i32 [ 1, %entry ], [ %i_plus_1, %body ]
   %g = bitcast [8 x i8]* @SzGlobal64 to i64*
   %i_64 = zext i32 %i to i64
   %unused = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %g, i64 %i_64, i64 %i_64, i32 6, i32 6)
   %i_plus_1 = add i32 %i, 1
   %cmp = icmp eq i32 %i_plus_1, 1001
   br i1 %cmp, label %done, label %body
 done:
   ret void
 }
 ; O2-LABEL: test_cmpxchg8b_regalloc
 ;;; eax and some other register will be used in the cmpxchg instruction.
 ; O2: lock cmpxchg8b QWORD PTR
 ;;; Make sure eax/ecx/edx/ebx aren't used again, e.g. as the induction variable.
-; O2-NOT: {{eax|ecx|edx|ebx}}
+; O2-NOT: ,{{eax|ecx|edx|ebx}}
 ; O2: pop ebx