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1 ; Tests various aspects of x86 opcode encodings. E.g., some opcodes like | 1 ; Tests various aspects of x86 opcode encodings. E.g., some opcodes like |
2 ; those for pmull vary more wildly depending on operand size (rather than | 2 ; those for pmull vary more wildly depending on operand size (rather than |
3 ; follow a usual pattern). | 3 ; follow a usual pattern). |
4 | 4 |
5 ; RUN: %p2i --filetype=obj --disassemble --sandbox -i %s --args -O2 \ | 5 ; RUN: %p2i --filetype=obj --disassemble --sandbox -i %s --args -O2 \ |
6 ; RUN: -mattr=sse4.1 | FileCheck %s | 6 ; RUN: -mattr=sse4.1 -split-local-vars=0 | FileCheck %s |
7 | 7 |
8 define internal <8 x i16> @test_mul_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) { | 8 define internal <8 x i16> @test_mul_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) { |
9 entry: | 9 entry: |
10 %res = mul <8 x i16> %arg0, %arg1 | 10 %res = mul <8 x i16> %arg0, %arg1 |
11 ret <8 x i16> %res | 11 ret <8 x i16> %res |
12 ; CHECK-LABEL: test_mul_v8i16 | 12 ; CHECK-LABEL: test_mul_v8i16 |
13 ; CHECK: 66 0f d5 c1 pmullw xmm0,xmm1 | 13 ; CHECK: 66 0f d5 c1 pmullw xmm0,xmm1 |
14 } | 14 } |
15 | 15 |
16 ; Test register and address mode encoding. | 16 ; Test register and address mode encoding. |
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298 three: | 298 three: |
299 %res3 = extractelement <8 x i16> %vec4, i32 7 | 299 %res3 = extractelement <8 x i16> %vec4, i32 7 |
300 %res3_ext = zext i16 %res3 to i32 | 300 %res3_ext = zext i16 %res3 to i32 |
301 ret i32 %res3_ext | 301 ret i32 %res3_ext |
302 } | 302 } |
303 ; CHECK-LABEL: test_pextrw | 303 ; CHECK-LABEL: test_pextrw |
304 ; CHECK-DAG: 66 0f c5 c0 00 pextrw eax,xmm0 | 304 ; CHECK-DAG: 66 0f c5 c0 00 pextrw eax,xmm0 |
305 ; CHECK-DAG: 66 0f c5 c1 02 pextrw eax,xmm1 | 305 ; CHECK-DAG: 66 0f c5 c1 02 pextrw eax,xmm1 |
306 ; CHECK-DAG: 66 0f c5 c2 05 pextrw eax,xmm2 | 306 ; CHECK-DAG: 66 0f c5 c2 05 pextrw eax,xmm2 |
307 ; CHECK-DAG: 66 0f c5 c3 07 pextrw eax,xmm3 | 307 ; CHECK-DAG: 66 0f c5 c3 07 pextrw eax,xmm3 |
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