| Index: src/IceTargetLowering.h
|
| diff --git a/src/IceTargetLowering.h b/src/IceTargetLowering.h
|
| index 43f5e01f176ba30d489544587932cb499618516e..50853d8a1841570e1674bfa4804e88c5f1981022 100644
|
| --- a/src/IceTargetLowering.h
|
| +++ b/src/IceTargetLowering.h
|
| @@ -23,11 +23,12 @@
|
| #ifndef SUBZERO_SRC_ICETARGETLOWERING_H
|
| #define SUBZERO_SRC_ICETARGETLOWERING_H
|
|
|
| -#include "IceDefs.h"
|
| #include "IceBitVector.h"
|
| #include "IceCfgNode.h"
|
| +#include "IceDefs.h"
|
| #include "IceInst.h" // for the names of the Inst subtypes
|
| #include "IceOperand.h"
|
| +#include "IceRegAlloc.h"
|
| #include "IceTypes.h"
|
|
|
| #include <utility>
|
| @@ -290,6 +291,7 @@ public:
|
| virtual const SmallBitVector &getAliasesForRegister(RegNumT) const = 0;
|
|
|
| void regAlloc(RegAllocKind Kind);
|
| + void postRegallocSplitting(const SmallBitVector &RegMask);
|
|
|
| virtual void
|
| makeRandomRegisterPermutation(llvm::SmallVectorImpl<RegNumT> &Permutation,
|
| @@ -321,6 +323,12 @@ public:
|
| virtual void addProlog(CfgNode *Node) = 0;
|
| virtual void addEpilog(CfgNode *Node) = 0;
|
|
|
| + virtual Inst *createLoweredMove(Variable *Dest, Variable *SrcVar) {
|
| + (void)Dest;
|
| + (void)SrcVar;
|
| + llvm_unreachable("unimplemented createLoweredMove");
|
| + }
|
| +
|
| virtual ~TargetLowering() = default;
|
|
|
| private:
|
|
|