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1 //===- subzero/src/IceRegAlloc.h - Linear-scan reg. allocation --*- C++ -*-===// | 1 //===- subzero/src/IceRegAlloc.h - Linear-scan reg. allocation --*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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25 | 25 |
26 namespace Ice { | 26 namespace Ice { |
27 | 27 |
28 class LinearScan { | 28 class LinearScan { |
29 LinearScan() = delete; | 29 LinearScan() = delete; |
30 LinearScan(const LinearScan &) = delete; | 30 LinearScan(const LinearScan &) = delete; |
31 LinearScan &operator=(const LinearScan &) = delete; | 31 LinearScan &operator=(const LinearScan &) = delete; |
32 | 32 |
33 public: | 33 public: |
34 explicit LinearScan(Cfg *Func); | 34 explicit LinearScan(Cfg *Func); |
35 void init(RegAllocKind Kind); | 35 void init(RegAllocKind Kind, CfgSet<Variable *> ExcludeVars = {}); |
36 void scan(const SmallBitVector &RegMask, bool Randomized); | 36 void scan(const SmallBitVector &RegMask, bool Randomized); |
37 // Returns the number of times some variable has been assigned a register but | 37 // Returns the number of times some variable has been assigned a register but |
38 // later evicted because of a higher-priority allocation. The idea is that we | 38 // later evicted because of a higher-priority allocation. The idea is that we |
39 // can implement "second-chance bin-packing" by rerunning register allocation | 39 // can implement "second-chance bin-packing" by rerunning register allocation |
40 // until there are no more evictions. | 40 // until there are no more evictions. |
41 SizeT getNumEvictions() const { return Evicted.size(); } | 41 SizeT getNumEvictions() const { return Evicted.size(); } |
42 bool hasEvictions() const { return !Evicted.empty(); } | 42 bool hasEvictions() const { return !Evicted.empty(); } |
43 void dump(Cfg *Func) const; | 43 void dump(Cfg *Func) const; |
44 | 44 |
45 // TODO(stichnot): Statically choose the size based on the target being | 45 // TODO(stichnot): Statically choose the size based on the target being |
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124 UnorderedRanges Evicted; | 124 UnorderedRanges Evicted; |
125 CfgVector<InstNumberT> Kills; | 125 CfgVector<InstNumberT> Kills; |
126 RegAllocKind Kind = RAK_Unknown; | 126 RegAllocKind Kind = RAK_Unknown; |
127 /// RegUses[I] is the number of live ranges (variables) that register I is | 127 /// RegUses[I] is the number of live ranges (variables) that register I is |
128 /// currently assigned to. It can be greater than 1 as a result of | 128 /// currently assigned to. It can be greater than 1 as a result of |
129 /// AllowOverlap inference. | 129 /// AllowOverlap inference. |
130 llvm::SmallVector<int32_t, REGS_SIZE> RegUses; | 130 llvm::SmallVector<int32_t, REGS_SIZE> RegUses; |
131 llvm::SmallVector<const SmallBitVector *, REGS_SIZE> RegAliases; | 131 llvm::SmallVector<const SmallBitVector *, REGS_SIZE> RegAliases; |
132 bool FindPreference = false; | 132 bool FindPreference = false; |
133 bool FindOverlap = false; | 133 bool FindOverlap = false; |
134 | |
135 const bool Verbose; | 134 const bool Verbose; |
136 const bool UseReserve; | 135 const bool UseReserve; |
| 136 CfgVector<Variable *> Vars; |
137 }; | 137 }; |
138 | 138 |
139 } // end of namespace Ice | 139 } // end of namespace Ice |
140 | 140 |
141 #endif // SUBZERO_SRC_ICEREGALLOC_H | 141 #endif // SUBZERO_SRC_ICEREGALLOC_H |
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