Subzero : Live Range Splitting after initial Register Allocation

src/IceTargetLowering.h

 //===- subzero/src/IceTargetLowering.h - Lowering interface -----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 11 matching lines @@
 
 #ifndef SUBZERO_SRC_ICETARGETLOWERING_H
 #define SUBZERO_SRC_ICETARGETLOWERING_H
 
 #include "IceDefs.h"
 #include "IceBitVector.h"
 #include "IceCfgNode.h"
 #include "IceInst.h" // for the names of the Inst subtypes
 #include "IceOperand.h"
 #include "IceTypes.h"
+#include "IceRegAlloc.h"

[Jim Stichnoth, 2016/07/29 17:04:07]

sort

[manasijm, 2016/08/01 22:20:05]

Done.

 
 #include <utility>
 
 namespace Ice {
 
 // UnimplementedError is defined as a macro so that we can get actual line
 // numbers.
 #define UnimplementedError(Flags)                                              \
   do {                                                                         \
     if (!static_cast<const ClFlags &>(Flags).getSkipUnimplemented()) {         \
@@ skipping 241 matching lines @@
   virtual const SmallBitVector &
   getRegistersForVariable(const Variable *Var) const = 0;
   /// Get the set of *all* physical registers available for the specified
   /// Variable's register class, *not* applying register restrictions from the
   /// command line.
   virtual const SmallBitVector &
   getAllRegistersForVariable(const Variable *Var) const = 0;
   virtual const SmallBitVector &getAliasesForRegister(RegNumT) const = 0;
 
   void regAlloc(RegAllocKind Kind);
+  void postRegallocSplitting(LinearScan &RegAllocator,
+                             const SmallBitVector &RegMask);
 
   virtual void
   makeRandomRegisterPermutation(llvm::SmallVectorImpl<RegNumT> &Permutation,
                                 const SmallBitVector &ExcludeRegisters,
                                 uint64_t Salt) const = 0;
 
   /// Get the minimum number of clusters required for a jump table to be
   /// considered.
   virtual SizeT getMinJumpTableSize() const = 0;
   virtual void emitJumpTable(const Cfg *Func,
@@ skipping 11 matching lines @@
   virtual void emit(const ConstantUndef *C) const = 0;
   virtual void emit(const ConstantRelocatable *CR) const = 0;
 
   /// Performs target-specific argument lowering.
   virtual void lowerArguments() = 0;
 
   virtual void initNodeForLowering(CfgNode *) {}
   virtual void addProlog(CfgNode *Node) = 0;
   virtual void addEpilog(CfgNode *Node) = 0;
 
+  virtual Inst *createLoweredMove(Variable *Dest, Variable *SrcVar) {
+    (void)Dest;
+    (void)SrcVar;
+    llvm_unreachable("unimplemented createLoweredMove");
+  }
+
   virtual ~TargetLowering() = default;
 
 private:
   // This control variable is used by AutoBundle (RAII-style bundle
   // locking/unlocking) to prevent nested bundles.
   bool AutoBundling = false;
 
   /// This indicates whether we are in the genTargetHelperCalls phase, and
   /// therefore can do things like scalarization.
   bool GeneratingTargetHelpers = false;
@@ skipping 287 matching lines @@
   virtual void lower() {}
 
 protected:
   explicit TargetHeaderLowering(GlobalContext *Ctx) : Ctx(Ctx) {}
   GlobalContext *Ctx;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERING_H