Subzero : Live Range Splitting after initial Register Allocation

src/IceRegAlloc.h

 //===- subzero/src/IceRegAlloc.h - Linear-scan reg. allocation --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 14 matching lines @@
 
 namespace Ice {
 
 class LinearScan {
   LinearScan() = delete;
   LinearScan(const LinearScan &) = delete;
   LinearScan &operator=(const LinearScan &) = delete;
 
 public:
   explicit LinearScan(Cfg *Func);
-  void init(RegAllocKind Kind);
+  void init(RegAllocKind Kind, CfgSet<Variable *> ExtraVars = {},
+            CfgSet<Variable *> ExcludeVars = {});
   void scan(const SmallBitVector &RegMask, bool Randomized);
   // Returns the number of times some variable has been assigned a register but
   // later evicted because of a higher-priority allocation.  The idea is that we
   // can implement "second-chance bin-packing" by rerunning register allocation
   // until there are no more evictions.
   SizeT getNumEvictions() const { return Evicted.size(); }
   bool hasEvictions() const { return !Evicted.empty(); }
+  void setSplittingMode() { SplittingMode = true; }
   void dump(Cfg *Func) const;
 
   // TODO(stichnot): Statically choose the size based on the target being
   // compiled.  For now, choose a value large enough to fit into the
   // SmallVector's fixed portion, which is 32 for x86-32, 84 for x86-64, and 102
   // for ARM32.
   static constexpr size_t REGS_SIZE = 128;
 
 private:
   using OrderedRanges = CfgVector<Variable *>;
@@ skipping 71 matching lines @@
   UnorderedRanges Evicted;
   CfgVector<InstNumberT> Kills;
   RegAllocKind Kind = RAK_Unknown;
   /// RegUses[I] is the number of live ranges (variables) that register I is
   /// currently assigned to. It can be greater than 1 as a result of
   /// AllowOverlap inference.
   llvm::SmallVector<int32_t, REGS_SIZE> RegUses;
   llvm::SmallVector<const SmallBitVector *, REGS_SIZE> RegAliases;
   bool FindPreference = false;
   bool FindOverlap = false;
-
   const bool Verbose;
   const bool UseReserve;
+  bool SplittingMode = false;
+  CfgVector<Variable *> Vars;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEREGALLOC_H