Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(155)

Issues Search
    My Issues | Starred     Open | Closed | All

Side by Side Diff: src/compiler/ia32/instruction-codes-ia32.h

Issue 2170343002: [turbofan] Change Float64Max/Float64Min to JavaScript semantics. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: mips/mips64 ports. Created 4 years, 5 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « src/compiler/ia32/code-generator-ia32.cc ('k') | src/compiler/ia32/instruction-scheduler-ia32.cc » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ 5 #ifndef V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
6 #define V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ 6 #define V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 30 matching lines...) Expand all
41 V(IA32SarPair) \ 41 V(IA32SarPair) \
42 V(IA32Ror) \ 42 V(IA32Ror) \
43 V(IA32Lzcnt) \ 43 V(IA32Lzcnt) \
44 V(IA32Tzcnt) \ 44 V(IA32Tzcnt) \
45 V(IA32Popcnt) \ 45 V(IA32Popcnt) \
46 V(SSEFloat32Cmp) \ 46 V(SSEFloat32Cmp) \
47 V(SSEFloat32Add) \ 47 V(SSEFloat32Add) \
48 V(SSEFloat32Sub) \ 48 V(SSEFloat32Sub) \
49 V(SSEFloat32Mul) \ 49 V(SSEFloat32Mul) \
50 V(SSEFloat32Div) \ 50 V(SSEFloat32Div) \
51 V(SSEFloat32Max) \
52 V(SSEFloat32Min) \
53 V(SSEFloat32Abs) \ 51 V(SSEFloat32Abs) \
54 V(SSEFloat32Neg) \ 52 V(SSEFloat32Neg) \
55 V(SSEFloat32Sqrt) \ 53 V(SSEFloat32Sqrt) \
56 V(SSEFloat32Round) \ 54 V(SSEFloat32Round) \
57 V(SSEFloat64Cmp) \ 55 V(SSEFloat64Cmp) \
58 V(SSEFloat64Add) \ 56 V(SSEFloat64Add) \
59 V(SSEFloat64Sub) \ 57 V(SSEFloat64Sub) \
60 V(SSEFloat64Mul) \ 58 V(SSEFloat64Mul) \
61 V(SSEFloat64Div) \ 59 V(SSEFloat64Div) \
62 V(SSEFloat64Mod) \ 60 V(SSEFloat64Mod) \
(...skipping 16 matching lines...) Expand all
79 V(SSEFloat64ExtractLowWord32) \ 77 V(SSEFloat64ExtractLowWord32) \
80 V(SSEFloat64ExtractHighWord32) \ 78 V(SSEFloat64ExtractHighWord32) \
81 V(SSEFloat64InsertLowWord32) \ 79 V(SSEFloat64InsertLowWord32) \
82 V(SSEFloat64InsertHighWord32) \ 80 V(SSEFloat64InsertHighWord32) \
83 V(SSEFloat64LoadLowWord32) \ 81 V(SSEFloat64LoadLowWord32) \
84 V(SSEFloat64SilenceNaN) \ 82 V(SSEFloat64SilenceNaN) \
85 V(AVXFloat32Add) \ 83 V(AVXFloat32Add) \
86 V(AVXFloat32Sub) \ 84 V(AVXFloat32Sub) \
87 V(AVXFloat32Mul) \ 85 V(AVXFloat32Mul) \
88 V(AVXFloat32Div) \ 86 V(AVXFloat32Div) \
89 V(AVXFloat32Max) \
90 V(AVXFloat32Min) \
91 V(AVXFloat64Add) \ 87 V(AVXFloat64Add) \
92 V(AVXFloat64Sub) \ 88 V(AVXFloat64Sub) \
93 V(AVXFloat64Mul) \ 89 V(AVXFloat64Mul) \
94 V(AVXFloat64Div) \ 90 V(AVXFloat64Div) \
95 V(AVXFloat64Max) \
96 V(AVXFloat64Min) \
97 V(AVXFloat64Abs) \ 91 V(AVXFloat64Abs) \
98 V(AVXFloat64Neg) \ 92 V(AVXFloat64Neg) \
99 V(AVXFloat32Abs) \ 93 V(AVXFloat32Abs) \
100 V(AVXFloat32Neg) \ 94 V(AVXFloat32Neg) \
101 V(IA32Movsxbl) \ 95 V(IA32Movsxbl) \
102 V(IA32Movzxbl) \ 96 V(IA32Movzxbl) \
103 V(IA32Movb) \ 97 V(IA32Movb) \
104 V(IA32Movsxwl) \ 98 V(IA32Movsxwl) \
105 V(IA32Movzxwl) \ 99 V(IA32Movzxwl) \
106 V(IA32Movw) \ 100 V(IA32Movw) \
(...skipping 43 matching lines...) Expand 10 before | Expand all | Expand 10 after
150 V(M2I) /* [ %r2*2 + K] */ \ 144 V(M2I) /* [ %r2*2 + K] */ \
151 V(M4I) /* [ %r2*4 + K] */ \ 145 V(M4I) /* [ %r2*4 + K] */ \
152 V(M8I) /* [ %r2*8 + K] */ \ 146 V(M8I) /* [ %r2*8 + K] */ \
153 V(MI) /* [ K] */ 147 V(MI) /* [ K] */
154 148
155 } // namespace compiler 149 } // namespace compiler
156 } // namespace internal 150 } // namespace internal
157 } // namespace v8 151 } // namespace v8
158 152
159 #endif // V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ 153 #endif // V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
OLDNEW
« no previous file with comments | « src/compiler/ia32/code-generator-ia32.cc ('k') | src/compiler/ia32/instruction-scheduler-ia32.cc » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698