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1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===// | 1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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413 void _xor(Variable *Dest, Variable *Src0, Variable *Src1) { | 413 void _xor(Variable *Dest, Variable *Src0, Variable *Src1) { |
414 Context.insert<InstMIPS32Xor>(Dest, Src0, Src1); | 414 Context.insert<InstMIPS32Xor>(Dest, Src0, Src1); |
415 } | 415 } |
416 | 416 |
417 void _xori(Variable *Dest, Variable *Src, uint32_t Imm) { | 417 void _xori(Variable *Dest, Variable *Src, uint32_t Imm) { |
418 Context.insert<InstMIPS32Xori>(Dest, Src, Imm); | 418 Context.insert<InstMIPS32Xori>(Dest, Src, Imm); |
419 } | 419 } |
420 | 420 |
421 void lowerArguments() override; | 421 void lowerArguments() override; |
422 | 422 |
| 423 /// Make a pass through the SortedSpilledVariables and actually assign stack |
| 424 /// slots. SpillAreaPaddingBytes takes into account stack alignment padding. |
| 425 /// The SpillArea starts after that amount of padding. This matches the scheme |
| 426 /// in getVarStackSlotParams, where there may be a separate multi-block global |
| 427 /// var spill area and a local var spill area. |
| 428 void assignVarStackSlots(VarList &SortedSpilledVariables, |
| 429 size_t SpillAreaPaddingBytes, |
| 430 size_t SpillAreaSizeBytes, |
| 431 size_t GlobalsAndSubsequentPaddingSize); |
| 432 |
423 /// Operand legalization helpers. To deal with address mode constraints, | 433 /// Operand legalization helpers. To deal with address mode constraints, |
424 /// the helpers will create a new Operand and emit instructions that | 434 /// the helpers will create a new Operand and emit instructions that |
425 /// guarantee that the Operand kind is one of those indicated by the | 435 /// guarantee that the Operand kind is one of those indicated by the |
426 /// LegalMask (a bitmask of allowed kinds). If the input Operand is known | 436 /// LegalMask (a bitmask of allowed kinds). If the input Operand is known |
427 /// to already meet the constraints, it may be simply returned as the result, | 437 /// to already meet the constraints, it may be simply returned as the result, |
428 /// without creating any new instructions or operands. | 438 /// without creating any new instructions or operands. |
429 enum OperandLegalization { | 439 enum OperandLegalization { |
430 Legal_None = 0, | 440 Legal_None = 0, |
431 Legal_Reg = 1 << 0, // physical register, not stack location | 441 Legal_Reg = 1 << 0, // physical register, not stack location |
432 Legal_Imm = 1 << 1, | 442 Legal_Imm = 1 << 1, |
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710 explicit TargetHeaderMIPS32(GlobalContext *Ctx); | 720 explicit TargetHeaderMIPS32(GlobalContext *Ctx); |
711 | 721 |
712 private: | 722 private: |
713 ~TargetHeaderMIPS32() = default; | 723 ~TargetHeaderMIPS32() = default; |
714 }; | 724 }; |
715 | 725 |
716 } // end of namespace MIPS32 | 726 } // end of namespace MIPS32 |
717 } // end of namespace Ice | 727 } // end of namespace Ice |
718 | 728 |
719 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H | 729 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H |
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