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| 1 // | 1 // |
| 2 // The Subzero Code Generator | 2 // The Subzero Code Generator |
| 3 // | 3 // |
| 4 // This file is distributed under the University of Illinois Open Source | 4 // This file is distributed under the University of Illinois Open Source |
| 5 // License. See LICENSE.TXT for details. | 5 // License. See LICENSE.TXT for details. |
| 6 // | 6 // |
| 7 //===----------------------------------------------------------------------===// | 7 //===----------------------------------------------------------------------===// |
| 8 /// | 8 /// |
| 9 /// \file | 9 /// \file |
| 10 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost | 10 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost |
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| 98 // Value is in bytes. Return Value adjusted to the next highest multiple of the | 98 // Value is in bytes. Return Value adjusted to the next highest multiple of the |
| 99 // stack alignment. | 99 // stack alignment. |
| 100 uint32_t applyStackAlignment(uint32_t Value) { | 100 uint32_t applyStackAlignment(uint32_t Value) { |
| 101 return Utils::applyAlignment(Value, MIPS32_STACK_ALIGNMENT_BYTES); | 101 return Utils::applyAlignment(Value, MIPS32_STACK_ALIGNMENT_BYTES); |
| 102 } | 102 } |
| 103 | 103 |
| 104 } // end of anonymous namespace | 104 } // end of anonymous namespace |
| 105 | 105 |
| 106 TargetMIPS32::TargetMIPS32(Cfg *Func) : TargetLowering(Func) {} | 106 TargetMIPS32::TargetMIPS32(Cfg *Func) : TargetLowering(Func) {} |
| 107 | 107 |
| 108 void TargetMIPS32::assignVarStackSlots(VarList &SortedSpilledVariables, |
| 109 size_t SpillAreaPaddingBytes, |
| 110 size_t SpillAreaSizeBytes, |
| 111 size_t GlobalsAndSubsequentPaddingSize) { |
| 112 const VariablesMetadata *VMetadata = Func->getVMetadata(); |
| 113 size_t GlobalsSpaceUsed = SpillAreaPaddingBytes; |
| 114 size_t NextStackOffset = SpillAreaPaddingBytes; |
| 115 CfgVector<size_t> LocalsSize(Func->getNumNodes()); |
| 116 const bool SimpleCoalescing = !callsReturnsTwice(); |
| 117 |
| 118 for (Variable *Var : SortedSpilledVariables) { |
| 119 size_t Increment = typeWidthInBytesOnStack(Var->getType()); |
| 120 if (SimpleCoalescing && VMetadata->isTracked(Var)) { |
| 121 if (VMetadata->isMultiBlock(Var)) { |
| 122 GlobalsSpaceUsed += Increment; |
| 123 NextStackOffset = GlobalsSpaceUsed; |
| 124 } else { |
| 125 SizeT NodeIndex = VMetadata->getLocalUseNode(Var)->getIndex(); |
| 126 LocalsSize[NodeIndex] += Increment; |
| 127 NextStackOffset = SpillAreaPaddingBytes + |
| 128 GlobalsAndSubsequentPaddingSize + |
| 129 LocalsSize[NodeIndex]; |
| 130 } |
| 131 } else { |
| 132 NextStackOffset += Increment; |
| 133 } |
| 134 Var->setStackOffset(SpillAreaSizeBytes - NextStackOffset); |
| 135 } |
| 136 } |
| 137 |
| 108 void TargetMIPS32::staticInit(GlobalContext *Ctx) { | 138 void TargetMIPS32::staticInit(GlobalContext *Ctx) { |
| 109 (void)Ctx; | 139 (void)Ctx; |
| 110 RegNumT::setLimit(RegMIPS32::Reg_NUM); | 140 RegNumT::setLimit(RegMIPS32::Reg_NUM); |
| 111 SmallBitVector IntegerRegisters(RegMIPS32::Reg_NUM); | 141 SmallBitVector IntegerRegisters(RegMIPS32::Reg_NUM); |
| 112 SmallBitVector I64PairRegisters(RegMIPS32::Reg_NUM); | 142 SmallBitVector I64PairRegisters(RegMIPS32::Reg_NUM); |
| 113 SmallBitVector Float32Registers(RegMIPS32::Reg_NUM); | 143 SmallBitVector Float32Registers(RegMIPS32::Reg_NUM); |
| 114 SmallBitVector Float64Registers(RegMIPS32::Reg_NUM); | 144 SmallBitVector Float64Registers(RegMIPS32::Reg_NUM); |
| 115 SmallBitVector VectorRegisters(RegMIPS32::Reg_NUM); | 145 SmallBitVector VectorRegisters(RegMIPS32::Reg_NUM); |
| 116 SmallBitVector InvalidRegisters(RegMIPS32::Reg_NUM); | 146 SmallBitVector InvalidRegisters(RegMIPS32::Reg_NUM); |
| 117 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ | 147 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ |
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| 846 uint32_t SpillAreaPaddingBytes = 0; | 876 uint32_t SpillAreaPaddingBytes = 0; |
| 847 uint32_t LocalsSlotsPaddingBytes = 0; | 877 uint32_t LocalsSlotsPaddingBytes = 0; |
| 848 alignStackSpillAreas(PreservedRegsSizeBytes, SpillAreaAlignmentBytes, | 878 alignStackSpillAreas(PreservedRegsSizeBytes, SpillAreaAlignmentBytes, |
| 849 GlobalsSize, LocalsSlotsAlignmentBytes, | 879 GlobalsSize, LocalsSlotsAlignmentBytes, |
| 850 &SpillAreaPaddingBytes, &LocalsSlotsPaddingBytes); | 880 &SpillAreaPaddingBytes, &LocalsSlotsPaddingBytes); |
| 851 SpillAreaSizeBytes += SpillAreaPaddingBytes + LocalsSlotsPaddingBytes; | 881 SpillAreaSizeBytes += SpillAreaPaddingBytes + LocalsSlotsPaddingBytes; |
| 852 uint32_t GlobalsAndSubsequentPaddingSize = | 882 uint32_t GlobalsAndSubsequentPaddingSize = |
| 853 GlobalsSize + LocalsSlotsPaddingBytes; | 883 GlobalsSize + LocalsSlotsPaddingBytes; |
| 854 | 884 |
| 855 // Adds the out args space to the stack, and align SP if necessary. | 885 // Adds the out args space to the stack, and align SP if necessary. |
| 856 TotalStackSizeBytes = PreservedRegsSizeBytes + SpillAreaSizeBytes + | 886 if (!NeedsStackAlignment) { |
| 857 FixedAllocaSizeBytes + | 887 SpillAreaSizeBytes += MaxOutArgsSizeBytes * (VariableAllocaUsed ? 0 : 1); |
| 858 (MaxOutArgsSizeBytes * (VariableAllocaUsed ? 0 : 1)); | 888 } else { |
| 889 uint32_t StackOffset = PreservedRegsSizeBytes; |
| 890 uint32_t StackSize = applyStackAlignment(StackOffset + SpillAreaSizeBytes); |
| 891 if (!VariableAllocaUsed) |
| 892 StackSize = applyStackAlignment(StackSize + MaxOutArgsSizeBytes); |
| 893 SpillAreaSizeBytes = StackSize - StackOffset; |
| 894 } |
| 895 |
| 896 // Combine fixed alloca with SpillAreaSize. |
| 897 SpillAreaSizeBytes += FixedAllocaSizeBytes; |
| 898 |
| 899 TotalStackSizeBytes = PreservedRegsSizeBytes + SpillAreaSizeBytes; |
| 859 | 900 |
| 860 // Generate "addiu sp, sp, -TotalStackSizeBytes" | 901 // Generate "addiu sp, sp, -TotalStackSizeBytes" |
| 861 if (TotalStackSizeBytes) { | 902 if (TotalStackSizeBytes) { |
| 862 // Use the scratch register if needed to legalize the immediate. | 903 // Use the scratch register if needed to legalize the immediate. |
| 863 Variable *SP = getPhysicalRegister(RegMIPS32::Reg_SP); | 904 Variable *SP = getPhysicalRegister(RegMIPS32::Reg_SP); |
| 864 _addiu(SP, SP, -(TotalStackSizeBytes)); | 905 _addiu(SP, SP, -(TotalStackSizeBytes)); |
| 865 } | 906 } |
| 866 | 907 |
| 867 Ctx->statsUpdateFrameBytes(TotalStackSizeBytes); | 908 Ctx->statsUpdateFrameBytes(TotalStackSizeBytes); |
| 868 | 909 |
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| 904 if (CC.argInReg(Ty, ArgNo, &DummyReg)) { | 945 if (CC.argInReg(Ty, ArgNo, &DummyReg)) { |
| 905 ArgNo++; | 946 ArgNo++; |
| 906 continue; | 947 continue; |
| 907 } else { | 948 } else { |
| 908 finishArgumentLowering(Arg, FP, TotalStackSizeBytes, &InArgsSizeBytes); | 949 finishArgumentLowering(Arg, FP, TotalStackSizeBytes, &InArgsSizeBytes); |
| 909 } | 950 } |
| 910 } | 951 } |
| 911 | 952 |
| 912 // Fill in stack offsets for locals. | 953 // Fill in stack offsets for locals. |
| 913 assignVarStackSlots(SortedSpilledVariables, SpillAreaPaddingBytes, | 954 assignVarStackSlots(SortedSpilledVariables, SpillAreaPaddingBytes, |
| 914 SpillAreaSizeBytes, GlobalsAndSubsequentPaddingSize, | 955 SpillAreaSizeBytes, GlobalsAndSubsequentPaddingSize); |
| 915 UsesFramePointer); | |
| 916 this->HasComputedFrame = true; | 956 this->HasComputedFrame = true; |
| 917 | 957 |
| 918 if (BuildDefs::dump() && Func->isVerbose(IceV_Frame)) { | 958 if (BuildDefs::dump() && Func->isVerbose(IceV_Frame)) { |
| 919 OstreamLocker _(Func->getContext()); | 959 OstreamLocker _(Func->getContext()); |
| 920 Ostream &Str = Func->getContext()->getStrDump(); | 960 Ostream &Str = Func->getContext()->getStrDump(); |
| 921 | 961 |
| 922 Str << "Stack layout:\n"; | 962 Str << "Stack layout:\n"; |
| 923 uint32_t SPAdjustmentPaddingSize = | 963 uint32_t SPAdjustmentPaddingSize = |
| 924 SpillAreaSizeBytes - LocalsSpillAreaSize - | 964 SpillAreaSizeBytes - LocalsSpillAreaSize - |
| 925 GlobalsAndSubsequentPaddingSize - SpillAreaPaddingBytes - | 965 GlobalsAndSubsequentPaddingSize - SpillAreaPaddingBytes - |
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| 2531 Str << "\t.set\t" | 2571 Str << "\t.set\t" |
| 2532 << "nomips16\n"; | 2572 << "nomips16\n"; |
| 2533 } | 2573 } |
| 2534 | 2574 |
| 2535 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; | 2575 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; |
| 2536 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; | 2576 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; |
| 2537 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; | 2577 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; |
| 2538 | 2578 |
| 2539 } // end of namespace MIPS32 | 2579 } // end of namespace MIPS32 |
| 2540 } // end of namespace Ice | 2580 } // end of namespace Ice |
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