S390: Fix convertion from int32 to float32

src/s390/assembler-s390.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 1388 matching lines @@
   uint32_t code = op << 16 | m3 * B12 | m4 * B8 | r1.code() * B4 | r2.code();
   emit4bytes(code);
 }
 
 // end of S390 Instruction generation
 
 // start of S390 instruction
 RX_FORM_EMIT(bc, BC)
 RR_FORM_EMIT(bctr, BCTR)
 RXE_FORM_EMIT(ceb, CEB)
-RRE_FORM_EMIT(cefbr, CEFBR)
 SS1_FORM_EMIT(ed, ED)
 RX_FORM_EMIT(ex, EX)
 RRE_FORM_EMIT(flogr, FLOGR)
 RRE_FORM_EMIT(lcgr, LCGR)
 RR_FORM_EMIT(lcr, LCR)
 RX_FORM_EMIT(le_z, LE)
 RXY_FORM_EMIT(ley, LEY)
 RIL1_FORM_EMIT(llihf, LLIHF)
 RIL1_FORM_EMIT(llilf, LLILF)
 RRE_FORM_EMIT(lngr, LNGR)
@@ skipping 1461 matching lines @@
                        Register r2) {
   DCHECK_EQ(m3, Condition(0));
   DCHECK_EQ(m4, Condition(0));
   rrfe_form(CELGBR, Condition(0), Condition(0), Register::from_code(r1.code()),
             r2);
 }
 
 // Convert from Fixed Logical (F32<-32)
 void Assembler::celfbr(Condition m3, Condition m4, DoubleRegister r1,
                        Register r2) {
-  DCHECK_EQ(m3, Condition(0));
   DCHECK_EQ(m4, Condition(0));
-  rrfe_form(CELFBR, Condition(0), Condition(0), Register::from_code(r1.code()),
-            r2);
+  rrfe_form(CELFBR, m3, Condition(0), Register::from_code(r1.code()), r2);
 }
 
 // Convert from Fixed Logical (L<-64)
 void Assembler::cdlgbr(Condition m3, Condition m4, DoubleRegister r1,
                        Register r2) {
   DCHECK_EQ(m3, Condition(0));
   DCHECK_EQ(m4, Condition(0));
   rrfe_form(CDLGBR, Condition(0), Condition(0), Register::from_code(r1.code()),
             r2);
 }
 
 // Convert from Fixed Logical (L<-32)
 void Assembler::cdlfbr(Condition m3, Condition m4, DoubleRegister r1,
                        Register r2) {
   DCHECK_EQ(m4, Condition(0));
   rrfe_form(CDLFBR, m3, Condition(0), Register::from_code(r1.code()), r2);
 }
 
 // Convert from Fixed point (S<-32)
-void Assembler::cefbr(DoubleRegister r1, Register r2) {
-  rre_form(CEFBR, Register::from_code(r1.code()), r2);
+void Assembler::cefbr(Condition m3, DoubleRegister r1, Register r2) {
+  rrfe_form(CEFBR, m3, Condition(0), Register::from_code(r1.code()), r2);
 }
 
 // Convert to Fixed point (32<-S)
 void Assembler::cfebr(Condition m3, Register r1, DoubleRegister r2) {
   rrfe_form(CFEBR, m3, Condition(0), r1, Register::from_code(r2.code()));
 }
 
 // Load (L <- S)
 void Assembler::ldeb(DoubleRegister d1, const MemOperand& opnd) {
   rxe_form(LDEB, Register::from_code(d1.code()), opnd.rx(), opnd.rb(),
@@ skipping 150 matching lines @@
                             SKIP_ICACHE_FLUSH);
     }
 
     reloc_info_writer.Write(&rinfo);
   }
 }
 
 }  // namespace internal
 }  // namespace v8
 #endif  // V8_TARGET_ARCH_S390