Subzero: Fix lowering for x86 div/rem instructions.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 2265 matching lines @@
       Edx = Traits::RegisterSet::Reg_dx;
       break;
     case IceType_i8:
       Eax = Traits::RegisterSet::Reg_al;
       Edx = Traits::RegisterSet::Reg_ah;
       break;
     }
     T_edx = makeReg(Ty, Edx);
     _mov(T, Src0, Eax);
     _mov(T_edx, Ctx->getConstantZero(Ty));
-    _div(T, Src1, T_edx);
+    _div(T_edx, Src1, T);
+    _redefined(Context.insert<InstFakeDef>(T, T_edx));
     _mov(Dest, T);
   } break;
   case InstArithmetic::Sdiv:
     // TODO(stichnot): Enable this after doing better performance and cross
     // testing.
     if (false && Func->getOptLevel() >= Opt_1) {
       // Optimize division by constant power of 2, but not for Om1 or O0, just
       // to keep things simple there.
       if (auto *C = llvm::dyn_cast<ConstantInteger32>(Src1)) {
         const int32_t Divisor = C->getValue();
@@ skipping 39 matching lines @@
     case IceType_i16:
       T_edx = makeReg(Ty, Traits::RegisterSet::Reg_dx);
       _mov(T, Src0, Traits::RegisterSet::Reg_ax);
       break;
     case IceType_i8:
       T_edx = makeReg(IceType_i16, Traits::RegisterSet::Reg_ax);
       _mov(T, Src0, Traits::RegisterSet::Reg_al);
       break;
     }
     _cbwdq(T_edx, T);
-    _idiv(T, Src1, T_edx);
+    _idiv(T_edx, Src1, T);
+    _redefined(Context.insert<InstFakeDef>(T, T_edx));
     _mov(Dest, T);
     break;
   case InstArithmetic::Urem: {
     Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
     RegNumT Eax;
     RegNumT Edx;
     switch (Ty) {
     default:
       llvm::report_fatal_error("Bad type for urem");
     case IceType_i64:
       Eax = Traits::getRaxOrDie();
       Edx = Traits::getRdxOrDie();
       break;
     case IceType_i32:
       Eax = Traits::RegisterSet::Reg_eax;
       Edx = Traits::RegisterSet::Reg_edx;
       break;
     case IceType_i16:
       Eax = Traits::RegisterSet::Reg_ax;
       Edx = Traits::RegisterSet::Reg_dx;
       break;
     case IceType_i8:
       Eax = Traits::RegisterSet::Reg_al;
       Edx = Traits::RegisterSet::Reg_ah;
       break;
     }
     T_edx = makeReg(Ty, Edx);
     _mov(T_edx, Ctx->getConstantZero(Ty));
     _mov(T, Src0, Eax);
-    _div(T_edx, Src1, T);
+    _div(T, Src1, T_edx);
+    _redefined(Context.insert<InstFakeDef>(T_edx, T));
     if (Ty == IceType_i8) {
       // Register ah must be moved into one of {al,bl,cl,dl} before it can be
       // moved into a general 8-bit register.
       auto *T_AhRcvr = makeReg(Ty);
       T_AhRcvr->setRegClass(RCX86_IsAhRcvr);
       _mov(T_AhRcvr, T_edx);
       T_edx = T_AhRcvr;
     }
     _mov(Dest, T_edx);
   } break;
@@ skipping 56 matching lines @@
       Edx = Traits::RegisterSet::Reg_dx;
       break;
     case IceType_i8:
       Eax = Traits::RegisterSet::Reg_al;
       Edx = Traits::RegisterSet::Reg_ah;
       break;
     }
     T_edx = makeReg(Ty, Edx);
     _mov(T, Src0, Eax);
     _cbwdq(T_edx, T);
-    _idiv(T_edx, Src1, T);
+    _idiv(T, Src1, T_edx);
+    _redefined(Context.insert<InstFakeDef>(T_edx, T));
     if (Ty == IceType_i8) {
       // Register ah must be moved into one of {al,bl,cl,dl} before it can be
       // moved into a general 8-bit register.
       auto *T_AhRcvr = makeReg(Ty);
       T_AhRcvr->setRegClass(RCX86_IsAhRcvr);
       _mov(T_AhRcvr, T_edx);
       T_edx = T_AhRcvr;
     }
     _mov(Dest, T_edx);
   } break;
@@ skipping 5570 matching lines @@
         emitGlobal(*Var, SectionSuffix);
       }
     }
   } break;
   }
 }
 } // end of namespace X86NAMESPACE
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H