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1 # Copyright 2015 The Chromium Authors. All rights reserved. | 1 # Copyright 2015 The Chromium Authors. All rights reserved. |
2 # Use of this source code is governed by a BSD-style license that can be | 2 # Use of this source code is governed by a BSD-style license that can be |
3 # found in the LICENSE file. | 3 # found in the LICENSE file. |
4 | 4 |
5 import("//build/config/v8_target_cpu.gni") | 5 import("//build/config/v8_target_cpu.gni") |
6 | 6 |
7 # These are primarily relevant in current_cpu == "mips*" contexts, where | 7 # These are primarily relevant in current_cpu == "mips*" contexts, where |
8 # MIPS code is being compiled. But they can also be relevant in the | 8 # MIPS code is being compiled. But they can also be relevant in the |
9 # other contexts when the code will change its behavior based on the | 9 # other contexts when the code will change its behavior based on the |
10 # cpu it wants to generate code for. | 10 # cpu it wants to generate code for. |
11 if (current_cpu == "mipsel" || v8_current_cpu == "mipsel") { | 11 if (current_cpu == "mipsel" || v8_current_cpu == "mipsel") { |
12 declare_args() { | 12 declare_args() { |
13 # MIPS arch variant. Possible values are: | 13 # MIPS arch variant. Possible values are: |
14 # "r1" | 14 # "r1" |
15 # "r2" | 15 # "r2" |
16 # "r6" | 16 # "r6" |
17 mips_arch_variant = "r1" | 17 mips_arch_variant = "r1" |
18 | 18 |
19 # MIPS DSP ASE revision. Possible values are: | 19 # MIPS DSP ASE revision. Possible values are: |
20 # 0: unavailable | 20 # 0: unavailable |
21 # 1: revision 1 | 21 # 1: revision 1 |
22 # 2: revision 2 | 22 # 2: revision 2 |
23 mips_dsp_rev = 0 | 23 mips_dsp_rev = 0 |
24 | 24 |
| 25 # MIPS SIMD Arch compilation flag. |
| 26 mips_use_msa = true |
| 27 |
25 # MIPS floating-point ABI. Possible values are: | 28 # MIPS floating-point ABI. Possible values are: |
26 # "hard": sets the GCC -mhard-float option. | 29 # "hard": sets the GCC -mhard-float option. |
27 # "soft": sets the GCC -msoft-float option. | 30 # "soft": sets the GCC -msoft-float option. |
28 mips_float_abi = "hard" | 31 mips_float_abi = "hard" |
29 | 32 |
30 # MIPS32 floating-point register width. Possible values are: | 33 # MIPS32 floating-point register width. Possible values are: |
31 # "fp32": sets the GCC -mfp32 option. | 34 # "fp32": sets the GCC -mfp32 option. |
32 # "fp64": sets the GCC -mfp64 option. | 35 # "fp64": sets the GCC -mfp64 option. |
33 # "fpxx": sets the GCC -mfpxx option. | 36 # "fpxx": sets the GCC -mfpxx option. |
34 mips_fpu_mode = "fp32" | 37 mips_fpu_mode = "fp32" |
35 } | 38 } |
36 } else if (current_cpu == "mips64el" || v8_current_cpu == "mips64el") { | 39 } else if (current_cpu == "mips64el" || v8_current_cpu == "mips64el") { |
37 # MIPS arch variant. Possible values are: | 40 # MIPS arch variant. Possible values are: |
38 # "r2" | 41 # "r2" |
39 # "r6" | 42 # "r6" |
40 if (current_os == "android" || target_os == "android") { | 43 if (current_os == "android" || target_os == "android") { |
41 declare_args() { | 44 declare_args() { |
42 mips_arch_variant = "r6" | 45 mips_arch_variant = "r6" |
| 46 |
| 47 # MIPS SIMD Arch compilation flag. |
| 48 mips_use_msa = true |
43 } | 49 } |
44 } else { | 50 } else { |
45 declare_args() { | 51 declare_args() { |
46 mips_arch_variant = "r2" | 52 mips_arch_variant = "r2" |
47 } | 53 } |
48 } | 54 } |
49 } | 55 } |
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