MIPS64: Implement Mips64And32, Mips64Or32, Mips64Nor32 and Mips64Xor32 operators.

test/unittests/compiler/mips64/instruction-selector-mips64-unittest.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file
 
 #include "test/unittests/compiler/instruction-selector-unittest.h"
 
 namespace v8 {
 namespace internal {
 namespace compiler {
 
@@ skipping 49 matching lines @@
   // The machine_type field in MachInst1 represents the destination type.
   MachInst1 mi;
   MachineType src_machine_type;
 };
 
 
 // ----------------------------------------------------------------------------
 // Logical instructions.
 // ----------------------------------------------------------------------------
 
-
 const MachInst2 kLogicalInstructions[] = {
-    {&RawMachineAssembler::Word32And, "Word32And", kMips64And,
+    {&RawMachineAssembler::Word32And, "Word32And", kMips64And32,
      MachineType::Int32()},
     {&RawMachineAssembler::Word64And, "Word64And", kMips64And,
      MachineType::Int64()},
-    {&RawMachineAssembler::Word32Or, "Word32Or", kMips64Or,
+    {&RawMachineAssembler::Word32Or, "Word32Or", kMips64Or32,
      MachineType::Int32()},
     {&RawMachineAssembler::Word64Or, "Word64Or", kMips64Or,
      MachineType::Int64()},
-    {&RawMachineAssembler::Word32Xor, "Word32Xor", kMips64Xor,
+    {&RawMachineAssembler::Word32Xor, "Word32Xor", kMips64Xor32,
      MachineType::Int32()},
     {&RawMachineAssembler::Word64Xor, "Word64Xor", kMips64Xor,
      MachineType::Int64()}};
 
-
 // ----------------------------------------------------------------------------
 // Shift instructions.
 // ----------------------------------------------------------------------------
 
 
 const MachInst2 kShiftInstructions[] = {
     {&RawMachineAssembler::Word32Shl, "Word32Shl", kMips64Shl,
      MachineType::Int32()},
     {&RawMachineAssembler::Word64Shl, "Word64Shl", kMips64Dshl,
      MachineType::Int64()},
@@ skipping 439 matching lines @@
   }
 }
 
 
 TEST_F(InstructionSelectorTest, Word32XorMinusOneWithParameter) {
   {
     StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
     m.Return(m.Word32Xor(m.Parameter(0), m.Int32Constant(-1)));
     Stream s = m.Build();
     ASSERT_EQ(1U, s.size());
-    EXPECT_EQ(kMips64Nor, s[0]->arch_opcode());
+    EXPECT_EQ(kMips64Nor32, s[0]->arch_opcode());
     EXPECT_EQ(2U, s[0]->InputCount());
     EXPECT_EQ(1U, s[0]->OutputCount());
   }
   {
     StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
     m.Return(m.Word32Xor(m.Int32Constant(-1), m.Parameter(0)));
     Stream s = m.Build();
     ASSERT_EQ(1U, s.size());
-    EXPECT_EQ(kMips64Nor, s[0]->arch_opcode());
+    EXPECT_EQ(kMips64Nor32, s[0]->arch_opcode());
     EXPECT_EQ(2U, s[0]->InputCount());
     EXPECT_EQ(1U, s[0]->OutputCount());
   }
 }
 
 
 TEST_F(InstructionSelectorTest, Word64XorMinusOneWithWord64Or) {
   {
     StreamBuilder m(this, MachineType::Int64(), MachineType::Int64());
     m.Return(m.Word64Xor(m.Word64Or(m.Parameter(0), m.Parameter(0)),
@@ skipping 17 matching lines @@
 }
 
 
 TEST_F(InstructionSelectorTest, Word32XorMinusOneWithWord32Or) {
   {
     StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
     m.Return(m.Word32Xor(m.Word32Or(m.Parameter(0), m.Parameter(0)),
                          m.Int32Constant(-1)));
     Stream s = m.Build();
     ASSERT_EQ(1U, s.size());
-    EXPECT_EQ(kMips64Nor, s[0]->arch_opcode());
+    EXPECT_EQ(kMips64Nor32, s[0]->arch_opcode());
     EXPECT_EQ(2U, s[0]->InputCount());
     EXPECT_EQ(1U, s[0]->OutputCount());
   }
   {
     StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
     m.Return(m.Word32Xor(m.Int32Constant(-1),
                          m.Word32Or(m.Parameter(0), m.Parameter(0))));
     Stream s = m.Build();
     ASSERT_EQ(1U, s.size());
-    EXPECT_EQ(kMips64Nor, s[0]->arch_opcode());
+    EXPECT_EQ(kMips64Nor32, s[0]->arch_opcode());
     EXPECT_EQ(2U, s[0]->InputCount());
     EXPECT_EQ(1U, s[0]->OutputCount());
   }
 }
 
 
 TEST_F(InstructionSelectorTest, Word32AndWithImmediateWithWord32Shr) {
   // The available shift operand range is `0 <= imm < 32`, but we also test
   // that immediates outside this range are handled properly (modulo-32).
   TRACED_FORRANGE(int32_t, shift, -32, 63) {
@@ skipping 861 matching lines @@
   ASSERT_EQ(1U, s.size());
   EXPECT_EQ(kMips64Float64Min, s[0]->arch_opcode());
   ASSERT_EQ(2U, s[0]->InputCount());
   ASSERT_EQ(1U, s[0]->OutputCount());
   EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8