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Side by Side Diff: src/compiler/mips64/instruction-codes-mips64.h

Issue 2147883002: MIPS64: Implement Mips64And32, Mips64Or32, Mips64Nor32 and Mips64Xor32 operators. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Address comments. Created 4 years, 5 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 14 matching lines...) Expand all
25 V(Mips64Dmul) \ 25 V(Mips64Dmul) \
26 V(Mips64Div) \ 26 V(Mips64Div) \
27 V(Mips64Ddiv) \ 27 V(Mips64Ddiv) \
28 V(Mips64DivU) \ 28 V(Mips64DivU) \
29 V(Mips64DdivU) \ 29 V(Mips64DdivU) \
30 V(Mips64Mod) \ 30 V(Mips64Mod) \
31 V(Mips64Dmod) \ 31 V(Mips64Dmod) \
32 V(Mips64ModU) \ 32 V(Mips64ModU) \
33 V(Mips64DmodU) \ 33 V(Mips64DmodU) \
34 V(Mips64And) \ 34 V(Mips64And) \
35 V(Mips64And32) \
35 V(Mips64Or) \ 36 V(Mips64Or) \
37 V(Mips64Or32) \
36 V(Mips64Nor) \ 38 V(Mips64Nor) \
39 V(Mips64Nor32) \
37 V(Mips64Xor) \ 40 V(Mips64Xor) \
41 V(Mips64Xor32) \
38 V(Mips64Clz) \ 42 V(Mips64Clz) \
39 V(Mips64Lsa) \ 43 V(Mips64Lsa) \
40 V(Mips64Dlsa) \ 44 V(Mips64Dlsa) \
41 V(Mips64Shl) \ 45 V(Mips64Shl) \
42 V(Mips64Shr) \ 46 V(Mips64Shr) \
43 V(Mips64Sar) \ 47 V(Mips64Sar) \
44 V(Mips64Ext) \ 48 V(Mips64Ext) \
45 V(Mips64Ins) \ 49 V(Mips64Ins) \
46 V(Mips64Dext) \ 50 V(Mips64Dext) \
47 V(Mips64Dins) \ 51 V(Mips64Dins) \
(...skipping 111 matching lines...) Expand 10 before | Expand all | Expand 10 after
159 #define TARGET_ADDRESSING_MODE_LIST(V) \ 163 #define TARGET_ADDRESSING_MODE_LIST(V) \
160 V(MRI) /* [%r0 + K] */ \ 164 V(MRI) /* [%r0 + K] */ \
161 V(MRR) /* [%r0 + %r1] */ 165 V(MRR) /* [%r0 + %r1] */
162 166
163 167
164 } // namespace compiler 168 } // namespace compiler
165 } // namespace internal 169 } // namespace internal
166 } // namespace v8 170 } // namespace v8
167 171
168 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 172 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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