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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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525 V(not) \ | 525 V(not) \ |
526 V(or) \ | 526 V(or) \ |
527 V(repmovs) \ | 527 V(repmovs) \ |
528 V(sbb) \ | 528 V(sbb) \ |
529 V(sub) \ | 529 V(sub) \ |
530 V(test) \ | 530 V(test) \ |
531 V(xchg) \ | 531 V(xchg) \ |
532 V(xor) | 532 V(xor) |
533 | 533 |
534 | 534 |
| 535 // Shift instructions on operands/registers with kPointerSize, kInt32Size and |
| 536 // kInt64Size. |
| 537 #define SHIFT_INSTRUCTION_LIST(V) \ |
| 538 V(rol, 0x0) \ |
| 539 V(ror, 0x1) \ |
| 540 V(rcl, 0x2) \ |
| 541 V(rcr, 0x3) \ |
| 542 V(shl, 0x4) \ |
| 543 V(shr, 0x5) \ |
| 544 V(sar, 0x7) \ |
| 545 |
| 546 |
535 class Assembler : public AssemblerBase { | 547 class Assembler : public AssemblerBase { |
536 private: | 548 private: |
537 // We check before assembling an instruction that there is sufficient | 549 // We check before assembling an instruction that there is sufficient |
538 // space to write an instruction and its relocation information. | 550 // space to write an instruction and its relocation information. |
539 // The relocation writer's position must be kGap bytes above the end of | 551 // The relocation writer's position must be kGap bytes above the end of |
540 // the generated instructions. This leaves enough space for the | 552 // the generated instructions. This leaves enough space for the |
541 // longest possible x64 instruction, 15 bytes, and the longest possible | 553 // longest possible x64 instruction, 15 bytes, and the longest possible |
542 // relocation information encoding, RelocInfoWriter::kMaxLength == 16. | 554 // relocation information encoding, RelocInfoWriter::kMaxLength == 16. |
543 // (There is a 15 byte limit on x64 instruction length that rules out some | 555 // (There is a 15 byte limit on x64 instruction length that rules out some |
544 // otherwise valid instructions.) | 556 // otherwise valid instructions.) |
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849 void decb(const Operand& dst); | 861 void decb(const Operand& dst); |
850 | 862 |
851 // Sign-extends rax into rdx:rax. | 863 // Sign-extends rax into rdx:rax. |
852 void cqo(); | 864 void cqo(); |
853 // Sign-extends eax into edx:eax. | 865 // Sign-extends eax into edx:eax. |
854 void cdq(); | 866 void cdq(); |
855 | 867 |
856 // Multiply rax by src, put the result in rdx:rax. | 868 // Multiply rax by src, put the result in rdx:rax. |
857 void mul(Register src); | 869 void mul(Register src); |
858 | 870 |
859 void rcl(Register dst, Immediate imm8) { | 871 #define DECLARE_SHIFT_INSTRUCTION(instruction, subcode) \ |
860 shift(dst, imm8, 0x2); | 872 void instruction##p(Register dst, Immediate imm8) { \ |
| 873 shift(dst, imm8, subcode, kPointerSize); \ |
| 874 } \ |
| 875 \ |
| 876 void instruction##l(Register dst, Immediate imm8) { \ |
| 877 shift(dst, imm8, subcode, kInt32Size); \ |
| 878 } \ |
| 879 \ |
| 880 void instruction##q(Register dst, Immediate imm8) { \ |
| 881 shift(dst, imm8, subcode, kInt64Size); \ |
| 882 } \ |
| 883 \ |
| 884 void instruction##p_cl(Register dst) { \ |
| 885 shift(dst, subcode, kPointerSize); \ |
| 886 } \ |
| 887 \ |
| 888 void instruction##l_cl(Register dst) { \ |
| 889 shift(dst, subcode, kInt32Size); \ |
| 890 } \ |
| 891 \ |
| 892 void instruction##q_cl(Register dst) { \ |
| 893 shift(dst, subcode, kInt64Size); \ |
861 } | 894 } |
862 | 895 SHIFT_INSTRUCTION_LIST(DECLARE_SHIFT_INSTRUCTION) |
863 void rol(Register dst, Immediate imm8) { | 896 #undef DECLARE_SHIFT_INSTRUCTION |
864 shift(dst, imm8, 0x0); | |
865 } | |
866 | |
867 void roll(Register dst, Immediate imm8) { | |
868 shift_32(dst, imm8, 0x0); | |
869 } | |
870 | |
871 void rcr(Register dst, Immediate imm8) { | |
872 shift(dst, imm8, 0x3); | |
873 } | |
874 | |
875 void ror(Register dst, Immediate imm8) { | |
876 shift(dst, imm8, 0x1); | |
877 } | |
878 | |
879 void rorl(Register dst, Immediate imm8) { | |
880 shift_32(dst, imm8, 0x1); | |
881 } | |
882 | |
883 void rorl_cl(Register dst) { | |
884 shift_32(dst, 0x1); | |
885 } | |
886 | 897 |
887 // Shifts dst:src left by cl bits, affecting only dst. | 898 // Shifts dst:src left by cl bits, affecting only dst. |
888 void shld(Register dst, Register src); | 899 void shld(Register dst, Register src); |
889 | 900 |
890 // Shifts src:dst right by cl bits, affecting only dst. | 901 // Shifts src:dst right by cl bits, affecting only dst. |
891 void shrd(Register dst, Register src); | 902 void shrd(Register dst, Register src); |
892 | 903 |
893 // Shifts dst right, duplicating sign bit, by shift_amount bits. | |
894 // Shifting by 1 is handled efficiently. | |
895 void sar(Register dst, Immediate shift_amount) { | |
896 shift(dst, shift_amount, 0x7); | |
897 } | |
898 | |
899 // Shifts dst right, duplicating sign bit, by shift_amount bits. | |
900 // Shifting by 1 is handled efficiently. | |
901 void sarl(Register dst, Immediate shift_amount) { | |
902 shift_32(dst, shift_amount, 0x7); | |
903 } | |
904 | |
905 // Shifts dst right, duplicating sign bit, by cl % 64 bits. | |
906 void sar_cl(Register dst) { | |
907 shift(dst, 0x7); | |
908 } | |
909 | |
910 // Shifts dst right, duplicating sign bit, by cl % 64 bits. | |
911 void sarl_cl(Register dst) { | |
912 shift_32(dst, 0x7); | |
913 } | |
914 | |
915 void shl(Register dst, Immediate shift_amount) { | |
916 shift(dst, shift_amount, 0x4); | |
917 } | |
918 | |
919 void shl_cl(Register dst) { | |
920 shift(dst, 0x4); | |
921 } | |
922 | |
923 void shll_cl(Register dst) { | |
924 shift_32(dst, 0x4); | |
925 } | |
926 | |
927 void shll(Register dst, Immediate shift_amount) { | |
928 shift_32(dst, shift_amount, 0x4); | |
929 } | |
930 | |
931 void shr(Register dst, Immediate shift_amount) { | |
932 shift(dst, shift_amount, 0x5); | |
933 } | |
934 | |
935 void shr_cl(Register dst) { | |
936 shift(dst, 0x5); | |
937 } | |
938 | |
939 void shrl_cl(Register dst) { | |
940 shift_32(dst, 0x5); | |
941 } | |
942 | |
943 void shrl(Register dst, Immediate shift_amount) { | |
944 shift_32(dst, shift_amount, 0x5); | |
945 } | |
946 | |
947 void store_rax(void* dst, RelocInfo::Mode mode); | 904 void store_rax(void* dst, RelocInfo::Mode mode); |
948 void store_rax(ExternalReference ref); | 905 void store_rax(ExternalReference ref); |
949 | 906 |
950 void subb(Register dst, Immediate src) { | 907 void subb(Register dst, Immediate src) { |
951 immediate_arithmetic_op_8(0x5, dst, src); | 908 immediate_arithmetic_op_8(0x5, dst, src); |
952 } | 909 } |
953 | 910 |
954 void testb(Register dst, Register src); | 911 void testb(Register dst, Register src); |
955 void testb(Register reg, Immediate mask); | 912 void testb(Register reg, Immediate mask); |
956 void testb(const Operand& op, Immediate mask); | 913 void testb(const Operand& op, Immediate mask); |
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1449 Immediate src); | 1406 Immediate src); |
1450 // Operate on a 32-bit word in memory or register. | 1407 // Operate on a 32-bit word in memory or register. |
1451 void immediate_arithmetic_op_32(byte subcode, | 1408 void immediate_arithmetic_op_32(byte subcode, |
1452 Register dst, | 1409 Register dst, |
1453 Immediate src); | 1410 Immediate src); |
1454 void immediate_arithmetic_op_32(byte subcode, | 1411 void immediate_arithmetic_op_32(byte subcode, |
1455 const Operand& dst, | 1412 const Operand& dst, |
1456 Immediate src); | 1413 Immediate src); |
1457 | 1414 |
1458 // Emit machine code for a shift operation. | 1415 // Emit machine code for a shift operation. |
1459 void shift(Register dst, Immediate shift_amount, int subcode); | 1416 void shift(Register dst, Immediate shift_amount, int subcode, int size); |
1460 void shift_32(Register dst, Immediate shift_amount, int subcode); | |
1461 // Shift dst by cl % 64 bits. | 1417 // Shift dst by cl % 64 bits. |
1462 void shift(Register dst, int subcode); | 1418 void shift(Register dst, int subcode, int size); |
1463 void shift_32(Register dst, int subcode); | |
1464 | 1419 |
1465 void emit_farith(int b1, int b2, int i); | 1420 void emit_farith(int b1, int b2, int i); |
1466 | 1421 |
1467 // labels | 1422 // labels |
1468 // void print(Label* L); | 1423 // void print(Label* L); |
1469 void bind_to(Label* L, int pos); | 1424 void bind_to(Label* L, int pos); |
1470 | 1425 |
1471 // record reloc info for current pc_ | 1426 // record reloc info for current pc_ |
1472 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); | 1427 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); |
1473 | 1428 |
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1833 private: | 1788 private: |
1834 Assembler* assembler_; | 1789 Assembler* assembler_; |
1835 #ifdef DEBUG | 1790 #ifdef DEBUG |
1836 int space_before_; | 1791 int space_before_; |
1837 #endif | 1792 #endif |
1838 }; | 1793 }; |
1839 | 1794 |
1840 } } // namespace v8::internal | 1795 } } // namespace v8::internal |
1841 | 1796 |
1842 #endif // V8_X64_ASSEMBLER_X64_H_ | 1797 #endif // V8_X64_ASSEMBLER_X64_H_ |
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