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| 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 | 4 |
| 5 #include "vm/globals.h" // NOLINT | 5 #include "vm/globals.h" // NOLINT |
| 6 #if defined(TARGET_ARCH_ARM64) | 6 #if defined(TARGET_ARCH_ARM64) |
| 7 | 7 |
| 8 #include "vm/assembler.h" | 8 #include "vm/assembler.h" |
| 9 #include "vm/cpu.h" | 9 #include "vm/cpu.h" |
| 10 #include "vm/longjump.h" | 10 #include "vm/longjump.h" |
| (...skipping 1225 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 1236 void Assembler::EnterStubFrame() { | 1236 void Assembler::EnterStubFrame() { |
| 1237 EnterDartFrame(0); | 1237 EnterDartFrame(0); |
| 1238 } | 1238 } |
| 1239 | 1239 |
| 1240 | 1240 |
| 1241 void Assembler::LeaveStubFrame() { | 1241 void Assembler::LeaveStubFrame() { |
| 1242 LeaveDartFrame(); | 1242 LeaveDartFrame(); |
| 1243 } | 1243 } |
| 1244 | 1244 |
| 1245 | 1245 |
| 1246 #ifndef PRODUCT |
| 1247 void Assembler::MaybeTraceAllocation(intptr_t cid, |
| 1248 Register temp_reg, |
| 1249 Label* trace) { |
| 1250 ASSERT(cid > 0); |
| 1251 intptr_t state_offset = ClassTable::StateOffsetFor(cid); |
| 1252 LoadIsolate(temp_reg); |
| 1253 intptr_t table_offset = |
| 1254 Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid); |
| 1255 ldr(temp_reg, Address(temp_reg, table_offset)); |
| 1256 AddImmediate(temp_reg, temp_reg, state_offset); |
| 1257 ldr(temp_reg, Address(temp_reg, 0)); |
| 1258 tsti(temp_reg, Immediate(ClassHeapStats::TraceAllocationMask())); |
| 1259 b(trace, NE); |
| 1260 } |
| 1261 |
| 1262 |
| 1246 void Assembler::UpdateAllocationStats(intptr_t cid, | 1263 void Assembler::UpdateAllocationStats(intptr_t cid, |
| 1247 Heap::Space space) { | 1264 Heap::Space space) { |
| 1248 ASSERT(cid > 0); | 1265 ASSERT(cid > 0); |
| 1249 intptr_t counter_offset = | 1266 intptr_t counter_offset = |
| 1250 ClassTable::CounterOffsetFor(cid, space == Heap::kNew); | 1267 ClassTable::CounterOffsetFor(cid, space == Heap::kNew); |
| 1251 LoadIsolate(TMP2); | 1268 LoadIsolate(TMP2); |
| 1252 intptr_t table_offset = | 1269 intptr_t table_offset = |
| 1253 Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid); | 1270 Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid); |
| 1254 ldr(TMP, Address(TMP2, table_offset)); | 1271 ldr(TMP, Address(TMP2, table_offset)); |
| 1255 AddImmediate(TMP2, TMP, counter_offset); | 1272 AddImmediate(TMP2, TMP, counter_offset); |
| (...skipping 19 matching lines...) Expand all Loading... |
| 1275 Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid); | 1292 Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid); |
| 1276 ldr(TMP, Address(TMP2, table_offset)); | 1293 ldr(TMP, Address(TMP2, table_offset)); |
| 1277 AddImmediate(TMP2, TMP, class_offset); | 1294 AddImmediate(TMP2, TMP, class_offset); |
| 1278 ldr(TMP, Address(TMP2, count_field_offset)); | 1295 ldr(TMP, Address(TMP2, count_field_offset)); |
| 1279 AddImmediate(TMP, TMP, 1); | 1296 AddImmediate(TMP, TMP, 1); |
| 1280 str(TMP, Address(TMP2, count_field_offset)); | 1297 str(TMP, Address(TMP2, count_field_offset)); |
| 1281 ldr(TMP, Address(TMP2, size_field_offset)); | 1298 ldr(TMP, Address(TMP2, size_field_offset)); |
| 1282 add(TMP, TMP, Operand(size_reg)); | 1299 add(TMP, TMP, Operand(size_reg)); |
| 1283 str(TMP, Address(TMP2, size_field_offset)); | 1300 str(TMP, Address(TMP2, size_field_offset)); |
| 1284 } | 1301 } |
| 1285 | 1302 #endif // !PRODUCT |
| 1286 | |
| 1287 void Assembler::MaybeTraceAllocation(intptr_t cid, | |
| 1288 Register temp_reg, | |
| 1289 Label* trace) { | |
| 1290 ASSERT(cid > 0); | |
| 1291 intptr_t state_offset = ClassTable::StateOffsetFor(cid); | |
| 1292 LoadIsolate(temp_reg); | |
| 1293 intptr_t table_offset = | |
| 1294 Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid); | |
| 1295 ldr(temp_reg, Address(temp_reg, table_offset)); | |
| 1296 AddImmediate(temp_reg, temp_reg, state_offset); | |
| 1297 ldr(temp_reg, Address(temp_reg, 0)); | |
| 1298 tsti(temp_reg, Immediate(ClassHeapStats::TraceAllocationMask())); | |
| 1299 b(trace, NE); | |
| 1300 } | |
| 1301 | 1303 |
| 1302 | 1304 |
| 1303 void Assembler::TryAllocate(const Class& cls, | 1305 void Assembler::TryAllocate(const Class& cls, |
| 1304 Label* failure, | 1306 Label* failure, |
| 1305 Register instance_reg, | 1307 Register instance_reg, |
| 1306 Register temp_reg) { | 1308 Register temp_reg) { |
| 1307 ASSERT(failure != NULL); | 1309 ASSERT(failure != NULL); |
| 1308 if (FLAG_inline_alloc) { | 1310 if (FLAG_inline_alloc) { |
| 1309 // If this allocation is traced, program will jump to failure path | 1311 // If this allocation is traced, program will jump to failure path |
| 1310 // (i.e. the allocation stub) which will allocate the object and trace the | 1312 // (i.e. the allocation stub) which will allocate the object and trace the |
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| 1426 add(base, array, Operand(index, LSL, shift)); | 1428 add(base, array, Operand(index, LSL, shift)); |
| 1427 } | 1429 } |
| 1428 const OperandSize size = Address::OperandSizeFor(cid); | 1430 const OperandSize size = Address::OperandSizeFor(cid); |
| 1429 ASSERT(Address::CanHoldOffset(offset, Address::Offset, size)); | 1431 ASSERT(Address::CanHoldOffset(offset, Address::Offset, size)); |
| 1430 return Address(base, offset, Address::Offset, size); | 1432 return Address(base, offset, Address::Offset, size); |
| 1431 } | 1433 } |
| 1432 | 1434 |
| 1433 } // namespace dart | 1435 } // namespace dart |
| 1434 | 1436 |
| 1435 #endif // defined TARGET_ARCH_ARM64 | 1437 #endif // defined TARGET_ARCH_ARM64 |
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