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Side by Side Diff: runtime/vm/assembler_arm.cc

Issue 2143153002: Don't track allocations in product mode. (Closed) Base URL: git@github.com:dart-lang/sdk.git@master
Patch Set: other archs Created 4 years, 5 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" // NOLINT 5 #include "vm/globals.h" // NOLINT
6 #if defined(TARGET_ARCH_ARM) 6 #if defined(TARGET_ARCH_ARM)
7 7
8 #include "vm/assembler.h" 8 #include "vm/assembler.h"
9 #include "vm/cpu.h" 9 #include "vm/cpu.h"
10 #include "vm/longjump.h" 10 #include "vm/longjump.h"
(...skipping 3219 matching lines...) Expand 10 before | Expand all | Expand 10 after
3230 void Assembler::EnterStubFrame() { 3230 void Assembler::EnterStubFrame() {
3231 EnterDartFrame(0); 3231 EnterDartFrame(0);
3232 } 3232 }
3233 3233
3234 3234
3235 void Assembler::LeaveStubFrame() { 3235 void Assembler::LeaveStubFrame() {
3236 LeaveDartFrame(); 3236 LeaveDartFrame();
3237 } 3237 }
3238 3238
3239 3239
3240 #ifndef PRODUCT
3241 void Assembler::MaybeTraceAllocation(intptr_t cid,
3242 Register temp_reg,
3243 Label* trace) {
3244 LoadAllocationStatsAddress(temp_reg, cid);
3245 const uword state_offset = ClassHeapStats::state_offset();
3246 ldr(temp_reg, Address(temp_reg, state_offset));
3247 tst(temp_reg, Operand(ClassHeapStats::TraceAllocationMask()));
3248 b(trace, NE);
3249 }
3250
3251
3240 void Assembler::LoadAllocationStatsAddress(Register dest, 3252 void Assembler::LoadAllocationStatsAddress(Register dest,
3241 intptr_t cid) { 3253 intptr_t cid) {
3242 ASSERT(dest != kNoRegister); 3254 ASSERT(dest != kNoRegister);
3243 ASSERT(dest != TMP); 3255 ASSERT(dest != TMP);
3244 ASSERT(cid > 0); 3256 ASSERT(cid > 0);
3245 const intptr_t class_offset = ClassTable::ClassOffsetFor(cid); 3257 const intptr_t class_offset = ClassTable::ClassOffsetFor(cid);
3246 LoadIsolate(dest); 3258 LoadIsolate(dest);
3247 intptr_t table_offset = 3259 intptr_t table_offset =
3248 Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid); 3260 Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid);
3249 ldr(dest, Address(dest, table_offset)); 3261 ldr(dest, Address(dest, table_offset));
3250 AddImmediate(dest, class_offset); 3262 AddImmediate(dest, class_offset);
3251 } 3263 }
3252 3264
3253 3265
3254 void Assembler::MaybeTraceAllocation(intptr_t cid,
3255 Register temp_reg,
3256 Label* trace) {
3257 LoadAllocationStatsAddress(temp_reg, cid);
3258 const uword state_offset = ClassHeapStats::state_offset();
3259 ldr(temp_reg, Address(temp_reg, state_offset));
3260 tst(temp_reg, Operand(ClassHeapStats::TraceAllocationMask()));
3261 b(trace, NE);
3262 }
3263
3264
3265 void Assembler::IncrementAllocationStats(Register stats_addr_reg, 3266 void Assembler::IncrementAllocationStats(Register stats_addr_reg,
3266 intptr_t cid, 3267 intptr_t cid,
3267 Heap::Space space) { 3268 Heap::Space space) {
3268 ASSERT(stats_addr_reg != kNoRegister); 3269 ASSERT(stats_addr_reg != kNoRegister);
3269 ASSERT(stats_addr_reg != TMP); 3270 ASSERT(stats_addr_reg != TMP);
3270 ASSERT(cid > 0); 3271 ASSERT(cid > 0);
3271 const uword count_field_offset = (space == Heap::kNew) ? 3272 const uword count_field_offset = (space == Heap::kNew) ?
3272 ClassHeapStats::allocated_since_gc_new_space_offset() : 3273 ClassHeapStats::allocated_since_gc_new_space_offset() :
3273 ClassHeapStats::allocated_since_gc_old_space_offset(); 3274 ClassHeapStats::allocated_since_gc_old_space_offset();
3274 const Address& count_address = Address(stats_addr_reg, count_field_offset); 3275 const Address& count_address = Address(stats_addr_reg, count_field_offset);
(...skipping 16 matching lines...) Expand all
3291 ClassHeapStats::allocated_size_since_gc_old_space_offset(); 3292 ClassHeapStats::allocated_size_since_gc_old_space_offset();
3292 const Address& count_address = Address(stats_addr_reg, count_field_offset); 3293 const Address& count_address = Address(stats_addr_reg, count_field_offset);
3293 const Address& size_address = Address(stats_addr_reg, size_field_offset); 3294 const Address& size_address = Address(stats_addr_reg, size_field_offset);
3294 ldr(TMP, count_address); 3295 ldr(TMP, count_address);
3295 AddImmediate(TMP, 1); 3296 AddImmediate(TMP, 1);
3296 str(TMP, count_address); 3297 str(TMP, count_address);
3297 ldr(TMP, size_address); 3298 ldr(TMP, size_address);
3298 add(TMP, TMP, Operand(size_reg)); 3299 add(TMP, TMP, Operand(size_reg));
3299 str(TMP, size_address); 3300 str(TMP, size_address);
3300 } 3301 }
3302 #endif // !PRODUCT
3301 3303
3302 3304
3303 void Assembler::TryAllocate(const Class& cls, 3305 void Assembler::TryAllocate(const Class& cls,
3304 Label* failure, 3306 Label* failure,
3305 Register instance_reg, 3307 Register instance_reg,
3306 Register temp_reg) { 3308 Register temp_reg) {
3307 ASSERT(failure != NULL); 3309 ASSERT(failure != NULL);
3308 if (FLAG_inline_alloc) { 3310 if (FLAG_inline_alloc) {
3309 ASSERT(instance_reg != temp_reg); 3311 ASSERT(instance_reg != temp_reg);
3310 ASSERT(temp_reg != IP); 3312 ASSERT(temp_reg != IP);
(...skipping 195 matching lines...) Expand 10 before | Expand all | Expand 10 after
3506 3508
3507 3509
3508 const char* Assembler::FpuRegisterName(FpuRegister reg) { 3510 const char* Assembler::FpuRegisterName(FpuRegister reg) {
3509 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); 3511 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
3510 return fpu_reg_names[reg]; 3512 return fpu_reg_names[reg];
3511 } 3513 }
3512 3514
3513 } // namespace dart 3515 } // namespace dart
3514 3516
3515 #endif // defined TARGET_ARCH_ARM 3517 #endif // defined TARGET_ARCH_ARM
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