Adds subract, move wide immediate instructions to ARM64.

runtime/vm/disassembler_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/disassembler.h"
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM64.
 #if defined(TARGET_ARCH_ARM64)
 #include "platform/assert.h"
 
@@ skipping 12 matching lines @@
 
   // Writes one disassembled instruction into 'buffer' (0-terminated).
   // Returns true if the instruction was successfully decoded, false otherwise.
   void InstructionDecode(uword pc);
 
  private:
   // Bottleneck functions to print into the out_buffer.
   void Print(const char* str);
 
   // Printing of common values.
-  void PrintRegister(int reg);
+  void PrintRegister(int reg, R31Type r31t);
   void PrintShiftExtendRm(Instr* instr);
   void PrintS(Instr* instr);
 
   // Handle formatting of instructions and their options.
   int FormatRegister(Instr* instr, const char* option);
   int FormatOption(Instr* instr, const char* format);
   void Format(Instr* instr, const char* format);
   void Unknown(Instr* instr);
 
   // Decode instructions.
@@ skipping 38 matching lines @@
 // See for example the command "objdump -d <binary file>".
 static const char* reg_names[kNumberOfCpuRegisters] = {
   "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
   "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
   "r24", "ip0", "ip1", "pp",  "ctx", "fp",  "lr",  "r31",
 };
 
 
 // Print the register name according to the active name converter.
-void ARM64Decoder::PrintRegister(int reg) {
+void ARM64Decoder::PrintRegister(int reg, R31Type r31t) {
   ASSERT(0 <= reg);
   ASSERT(reg < kNumberOfCpuRegisters);
-  Print(reg_names[reg]);
+  if ((reg == 31)) {
+    const char* rstr = (r31t == R31IsZR) ? "zr" : "sp";
+    Print(rstr);
+  } else {
+    Print(reg_names[reg]);
+  }
 }
 
 
 // These shift names are defined in a way to match the native disassembler
 // formatting. See for example the command "objdump -d <binary file>".
 static const char* shift_names[kMaxShift] = {
   "lsl", "lsr", "asr", "ror"
 };
 
 
 static const char* extend_names[kMaxExtend] = {
   "uxtb", "uxth", "uxtw", "uxtx",
   "sxtb", "sxth", "sxtw", "sxtx",
 };
 
 
 // Print the register shift operands for the instruction. Generally used for
 // data processing instructions.
 void ARM64Decoder::PrintShiftExtendRm(Instr* instr) {
   int rm = instr->RmField();
   Shift shift = instr->ShiftTypeField();
   int shift_amount = instr->ShiftAmountField();
   Extend extend = instr->ExtendTypeField();
   int extend_shift_amount = instr->ExtShiftAmountField();
 
-  PrintRegister(rm);
+  PrintRegister(rm, R31IsZR);
 
   if (instr->IsShift() && (shift == LSL) && (shift_amount == 0)) {
     // Special case for using rm only.
     return;
   }
   if (instr->IsShift()) {
     // by immediate
     if ((shift == ROR) && (shift_amount == 0)) {
-      Print(", RRX");
+      Print(" RRX");
       return;
     } else if (((shift == LSR) || (shift == ASR)) && (shift_amount == 0)) {
       shift_amount = 32;
     }
     buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
                                remaining_size_in_buffer(),
-                               ", %s #%d",
+                               " %s #%d",
                                shift_names[shift],
                                shift_amount);
   } else {
     ASSERT(instr->IsExtend());
     // by register
     buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
                                remaining_size_in_buffer(),
-                               ", %s",
+                               " %s",
                                extend_names[extend]);
     if (((instr->SFField() == 1) && (extend == UXTX)) ||
         ((instr->SFField() == 0) && (extend == UXTW))) {
       // Shift amount.
       buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
                                  remaining_size_in_buffer(),
                                  " %d",
                                  extend_shift_amount);
     }
   }
 }
 
 
 // Handle all register based formatting in these functions to reduce the
 // complexity of FormatOption.
 int ARM64Decoder::FormatRegister(Instr* instr, const char* format) {
   ASSERT(format[0] == 'r');
   if (format[1] == 'n') {  // 'rn: Rn register
     int reg = instr->RnField();
-    PrintRegister(reg);
+    PrintRegister(reg, instr->RnMode());
     return 2;
   } else if (format[1] == 'd') {  // 'rd: Rd register
     int reg = instr->RdField();
-    PrintRegister(reg);
+    PrintRegister(reg, instr->RdMode());
     return 2;
   } else if (format[1] == 'm') {  // 'rm: Rm register
     int reg = instr->RmField();
-    PrintRegister(reg);
+    PrintRegister(reg, R31IsZR);
     return 2;
   }
   UNREACHABLE();
   return -1;
 }
 
 
 // FormatOption takes a formatting string and interprets it based on
 // the current instructions. The format string points to the first
 // character of the option string (the option escape has already been
@@ skipping 46 matching lines @@
           Print("s");
         }
         return 1;
       } else {
         UNREACHABLE();
       }
     }
     case 'r': {
       return FormatRegister(instr, format);
     }
+    case 'h': {
+      ASSERT(STRING_STARTS_WITH(format, "hw"));
+      const int shift = instr->HWField() << 4;
+      if (shift != 0) {
+        buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
+                                   remaining_size_in_buffer(),
+                                   "lsl %d",
+                                   shift);
+      }
+      return 2;
+    }
     default: {
       UNREACHABLE();
       break;
     }
   }
   UNREACHABLE();
   return -1;
 }
 
 
@@ skipping 17 matching lines @@
 // For currently unimplemented decodings the disassembler calls Unknown(instr)
 // which will just print "unknown" of the instruction bits.
 void ARM64Decoder::Unknown(Instr* instr) {
   Format(instr, "unknown");
 }
 
 
 void ARM64Decoder::DecodeMoveWide(Instr* instr) {
   switch (instr->Bits(29, 2)) {
     case 0:
-      Format(instr, "movn'sf 'rd, 'imm16");
+      Format(instr, "movn'sf 'rd, 'imm16 'hw");
       break;
     case 2:
-      Format(instr, "movz'sf 'rd, 'imm16");
+      Format(instr, "movz'sf 'rd, 'imm16 'hw");
       break;
     case 3:
-      Format(instr, "movk'sf 'rd, 'imm16");
+      Format(instr, "movk'sf 'rd, 'imm16 'hw");
       break;
     default:
       Unknown(instr);
       break;
   }
 }
 
 
 void ARM64Decoder::DecodeAddSubImm(Instr* instr) {
   switch (instr->Bit(30)) {
@@ skipping 183 matching lines @@
                                   human_buffer,
                                   sizeof(human_buffer),
                                   pc);
     pc += instruction_length;
   }
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM