Adds subract, move wide immediate instructions to ARM64.

runtime/vm/assembler_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_ARM64_H_
 #define VM_ASSEMBLER_ARM64_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_arm64.h directly; use assembler.h instead.
 #endif
@@ skipping 100 matching lines @@
   Operand() : encoding_(-1), type_(Unknown) { }
 
   // Data-processing operands - Copy constructor.
   Operand(const Operand& other)
       : ValueObject(), encoding_(other.encoding_), type_(other.type_) { }
 
   explicit Operand(Register rm) {
     ASSERT((rm != R31) && (rm != SP));
     const Register crm = ConcreteRegister(rm);
     encoding_ = (static_cast<int32_t>(crm) << kRmShift);
+    type_ = Shifted;
   }
 
   Operand(Register rm, Shift shift, int32_t imm) {
     ASSERT(Utils::IsUint(6, imm));
     ASSERT((rm != R31) && (rm != SP));
     const Register crm = ConcreteRegister(rm);
     encoding_ =
         (imm << kImm6Shift) |
         (static_cast<int32_t>(crm) << kRmShift) |
         (static_cast<int32_t>(shift) << kShiftTypeShift);
@@ skipping 121 matching lines @@
   static const intptr_t kEntryPointToPcMarkerOffset = 0;
 
   // Emit data (e.g encoded instruction or immediate) in instruction stream.
   void Emit(int32_t value);
 
   // On some other platforms, we draw a distinction between safe and unsafe
   // smis.
   static bool IsSafe(const Object& object) { return true; }
   static bool IsSafeSmi(const Object& object) { return object.IsSmi(); }
 
+  // Addition and subtraction.
   void add(Register rd, Register rn, Operand o) {
     AddSubHelper(kDoubleWord, false, false, rd, rn, o);
   }
   void addw(Register rd, Register rn, Operand o) {
     AddSubHelper(kWord, false, false, rd, rn, o);
   }
+  void sub(Register rd, Register rn, Operand o) {
+    AddSubHelper(kDoubleWord, false, true, rd, rn, o);
+  }
+
+  // Move wide immediate.
+  void movk(Register rd, int32_t imm, int32_t hw_idx) {
+    ASSERT(rd != SP);
+    const Register crd = ConcreteRegister(rd);
+    EmitMoveWideOp(MOVK, crd, imm, hw_idx, kDoubleWord);
+  }
+  void movn(Register rd, int32_t imm, int32_t hw_idx) {
+    ASSERT(rd != SP);
+    const Register crd = ConcreteRegister(rd);
+    EmitMoveWideOp(MOVN, crd, imm, hw_idx, kDoubleWord);
+  }
+  void movz(Register rd, int32_t imm, int32_t hw_idx) {
+    ASSERT(rd != SP);
+    const Register crd = ConcreteRegister(rd);
+    EmitMoveWideOp(MOVZ, crd, imm, hw_idx, kDoubleWord);
+  }
+
 
   // Function return.
   void ret(Register rn = R30) {
     EmitUnconditionalBranchRegOp(RET, rn);
   }
 
  private:
   AssemblerBuffer buffer_;  // Contains position independent code.
   GrowableObjectArray& object_pool_;  // Objects and patchable jump targets.
   int32_t prologue_offset_;
@@ skipping 18 matching lines @@
   GrowableArray<CodeComment*> comments_;
 
   void AddSubHelper(OperandSize os, bool set_flags, bool subtract,
                     Register rd, Register rn, Operand o) {
     ASSERT((rd != R31) && (rn != R31));
     const Register crd = ConcreteRegister(rd);
     const Register crn = ConcreteRegister(rn);
     if (o.type() == Operand::Immediate) {
       ASSERT((rd != ZR) && (rn != ZR));
       EmitAddSubImmOp(subtract ? SUBI : ADDI, crd, crn, o, os, set_flags);
+    } else if (o.type() == Operand::Shifted) {
+      ASSERT((rd != SP) && (rn != SP));
+      EmitAddSubShiftExtOp(subtract ? SUB : ADD, crd, crn, o, os, set_flags);
     } else {
-      if (o.type() == Operand::Shifted) {
-        ASSERT((rd != SP) && (rn != SP));
-        EmitAddSubShiftExtOp(subtract ? SUB : ADD, crd, crn, o, os, set_flags);
-      } else {
-        ASSERT(o.type() == Operand::Extended);
-        ASSERT((rd != SP) && (rn != ZR));
-        EmitAddSubShiftExtOp(subtract ? SUB : ADD, crd, crn, o, os, set_flags);
-      }
+      ASSERT(o.type() == Operand::Extended);
+      ASSERT((rd != SP) && (rn != ZR));
+      EmitAddSubShiftExtOp(subtract ? SUB : ADD, crd, crn, o, os, set_flags);
     }
   }
 
   void EmitAddSubImmOp(AddSubImmOp op, Register rd, Register rn,
                        Operand o, OperandSize os, bool set_flags) {
     ASSERT((os == kDoubleWord) || (os == kWord));
     const int32_t size = (os == kDoubleWord) ? B31 : 0;
     const int32_t s = set_flags ? B29 : 0;
     const int32_t encoding =
         op | size | s |
         (static_cast<int32_t>(rd) << kRdShift) |
         (static_cast<int32_t>(rn) << kRnShift) |
         o.encoding();
     Emit(encoding);
   }
 
   void EmitAddSubShiftExtOp(AddSubShiftExtOp op,
                             Register rd, Register rn, Operand o,
-                            OperandSize os, bool set_flags) {
-    ASSERT((os == kDoubleWord) || (os == kWord));
-    const int32_t size = (os == kDoubleWord) ? B31 : 0;
+                            OperandSize sz, bool set_flags) {
+    ASSERT((sz == kDoubleWord) || (sz == kWord));
+    const int32_t size = (sz == kDoubleWord) ? B31 : 0;
     const int32_t s = set_flags ? B29 : 0;
     const int32_t encoding =
         op | size | s |
         (static_cast<int32_t>(rd) << kRdShift) |
         (static_cast<int32_t>(rn) << kRnShift) |
         o.encoding();
     Emit(encoding);
   }
 
   void EmitUnconditionalBranchRegOp(UnconditionalBranchRegOp op, Register rn) {
     const int32_t encoding =
         op | (static_cast<int32_t>(rn) << kRnShift);
     Emit(encoding);
   }
 
+  void EmitMoveWideOp(MoveWideOp op, Register rd, int32_t imm, int32_t hw_idx,
+                      OperandSize sz) {
+    ASSERT(Utils::IsUint(16, imm));
+    ASSERT((hw_idx >= 0) && (hw_idx <= 3));
+    ASSERT((sz == kDoubleWord) || (sz == kWord));
+    const int32_t size = (sz == kDoubleWord) ? B31 : 0;
+    const int32_t encoding =
+        op | size |
+        (static_cast<int32_t>(rd) << kRdShift) |
+        (hw_idx << kHWShift) |
+        (imm << kImm16Shift);
+    Emit(encoding);
+  }
+
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_ARM64_H_